Radius Corporation

Douglas J Gilbert

Forrest Jean North

Timothy S Cale

Martin Randall

Joel Patrick Hanna

Ali Djabbari

Paul Campbell

Michael J Smith

Paul Greenland

A programmable CPU running at a video display rate, or a sub-multiple thereof, is used to generate the timings by loading control registers on the fly. In a preferred embodiment, a very reduced instruction set is used to generate VSYNC, HSYNC, and CSYNC signals. The CPU executes instructions out of an Instruction SRAM. The CPU's main goal is to load a pair of backing registers before a down counter reaches the value of zero.

Video timing signal generation circuit

A method and apparatus for performing transparent data transfer operations on graphics data (such as video data), in which a source image currently displayed as part of a destination image (or stored in memory) is moved to a selected destination location on the destination image without obliterating background portions of the destination image. In a class of embodiments, the invention accomplishes a transparent bit-block transfer by clocking out source data (stored in an internal memory) to a bank of arithmetic logic units (ALUs), and processing the source data in the ALUs to identify portions of the source data representing transparent (or background) data which should not replace corresponding destination data, and which represent foreground data (new text to replace destination data). The marked source data are selectively written into a video memory containing the destination data, to selectively overwrite only those destination data pixels corresponding to new text. Transfers of source data to individual video memory locations which correspond transparent (background) data are inhibited or aborted.

Method and apparatus for superimposing displayed images

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Davenport, IA, United States of America

Douglas J Gilbert