Analog Devices,inc.

Sypris Electronics, LLC

Digital Lightwave, Inc.

Douglas J Gardner

John Ross Wallrabenstein

John J Walsh

Kenneth T Myers

Various examples described herein are directed to power supplies and methods of operating power supplies. A power supply may comprise a regulator circuit configured to generate an output electrical signal and a sensor configured to generate a sensor signal describing the output electrical signal. The power supply may also comprise at least one processor that is programmed to determine that the sensor signal fails to match expected system profile data describing an operation of at least one component electrically coupled to the power supply. Responsive to determining that the sensor signal fails to match the expected system profile data, the at the least one processor may be programmed to execute a remedial action.

Power supply with system monitoring

One or more hardware identity circuits (which may be reconfigurable) may be employed in a device or system in order to impose a tampering penalty, preferably without relying on battery-backed volatile memory to do so. The device or system may also include a cryptographic division and distribution ('sharing') of a secret internal to the device or system.

System and device employing physical unclonable functions for tamper penalties

A hardware-locked encrypted backup (HWLE-BU) that is locked to a single hardware device using the device's unique hardware identity, based on a Physically-Unclonable Function (PUF) or other suitable means providing a unique hardware identity. The HWLE-BU is bound to a specific hardware identity such that only the physical device that created the HWLE-BU can decrypt it, i.e., restoring HWLE-BU data requires utilizing the same physical hardware device in the decryption process.

Hardware-locked encrypted backup

A system and device for verifying the integrity of a system from its subcomponents, the system comprising a plurality of subcomponents each having a physical state, the system and the device comprising a processor that is connected to each of the subcomponents, the processor configured to verify systemic integrity by performing verification on some or all specified subcomponents. The verification may be individual (1,1) or threshold (n,1), and may be interactive or non-interactive.

System and device for verifying the integrity of a system from its subcomponents

A multi-mode Trusted Computing Platform (TCP) comprising a Field Programmable Gate Array (FPGA) device that includes a Type-1-compliant root of trust (ROT), a memory containing a Type-1 security boot image and at least one lower-security boot image, and a memory containing a Type-1-associated operating system (OS) image and at least one lower-security-associated OS image. The TCP is configured to execute a multi-stage boot process that, depending on the presence of one or more valid external inputs, selects and initiates either a Type-1 TCP computing mode or a lower-assurance computing mode.

Multi-level assurance trusted computing platform

A protocol and bit rate independent test system for detecting bit errors on a digital communications channel regardless of format or rate, comprising a receiver for receiving an input, a clock recovery unit, a threshold sampling circuit for providing at least two threshold detectors for respective two sampling points including at least one static sampling point positioned proximate to the center of an eye pattern and at least one dynamic sampling point, the output of which are sampled by the recovered clock and if the signal passes between the thresholds, an error signal is generated and counted.

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Palm Harbor, FL, United States of America

Douglas J Gardner