Mosaid Technologies Corporation

General Electric Company

Ge Medical Systems Global Technology Company, LLC

Douglas I Perry

Peter B Gillingham

Scott William Petrick

Peter Vlasenko

Roland Frederick Saunders

Jin-Ki Kim

Alan S Roth

Habib Vafi

John Moore Boudry

Richard Gordon Cronce

Richard Foss

A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportional to its ML capacitance, and proportional to the current. Conventional ternary CAM cells have many matchline transistors, each contributing to the matchline capacitance. Embodiments of the present invention have a single matchline transistor between a matchline and a ground line, or tail-line, of the CAM cell. The single matchline transistor couples the matchline to the tail-line in response to a discharge signal from a compare circuit. The compare circuit can be divided into a pull-up section for driving a gate voltage level control node and a discharge section for discharging the gate voltage level control node, the discharge signal being provided at the gate voltage level control node.

Compare circuit for a content addressable memory cell

A pixel sensing subsystem for a solid state image sensor includes frame timing logic that produces a frame timing signal indicative of an end-of-frame time and a beginning-of-frame time and reset logic that produces a reset signal for a charge accumulator of pixel sensing electronics. The reset logic asserts the reset signal at least once between the end-of-frame time and the beginning-of-frame time to prevent saturation of the pixel sensing element.

Method and apparatus for preventing image artifacts

Ternary CAM cell for reduced matchline capacitance

A pixel sensing subsystem () for a solid state image sensor includes frame timing logic () that produces a frame timing signal indicative of an end-of-frame time and a beginning-of-frame time and reset logic () that produces a reset signal for a charge accumulator of pixel sensing electronics. The reset logic () asserts the reset signal at least once between the end-of-frame time and the beginning-of-frame time to prevent saturation of the pixel sensing element.

A method for replacing a defective row in a CAM array, the array having a plurality of normal rows of cells and at least one spare row of cells, each the row being enabled by a corresponding word line signal, and having corresponding match line outputs switched to corresponding ones of a plurality of match line inputs in a match line decoder, the method comprising the steps of: (a) generating a signal indicative of the location of a defective row in the array; (b) generating a set of word line select signals for selecting ones of the plurality of normal rows; (d) using the defective row signal to switch a word line select signal of the defective row to a row adjacent the defective row and switching the adjacent row word line select signals to subsequent rows upto the at least one spare row, and (e) using the defective row signal to switch the match line input of the row adjacent the defective row to the matchline input of the defective row and switching the subsequent row match line input to the adjacent row match line input, repeating the switching for subsequent matchlines upto the matchline of the at least one spare row.

Method and apparatus for replacing defective rows in a semiconductor memory array

A matchline sense circuit for detecting a current on a matchline of a CAM array is disclosed. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins. More specifically, a matchline sense circuit sense node receives a reference current, which is high enough to maintain the sense node at the high logic level. This reference current is generated from a dummy pull-down path identical to a memory cell pull-down path to ensure that the reference current tracks with changes to the memory cell current. Matchlines initially at ground potential undergo accelerated precharge up to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines for conserving power. During sensing, the matchline current is compared to the reference current, and a latch circuit connected to the sense node provides a full CMOS output signal indicating the result of the comparison. Reference matchlines are used to generate timed control signals for enabling the latch circuits.

Matchline sensing for content addressable memories

A method and apparatus for correcting the offset induced by Field Effect Transistor (FET) photo-conductive effects in solid state x-ray detectors includes dedicating rows at the beginning and end of an x-ray detector scan. The dedicated rows may be used to measure the &ldquo;signal&rdquo; induced by the photo-conductivity of FET switches in solid state x-ray detectors. Since the signal induced by FET photo-conductivity decays over time, the measurements taken at the beginning and end of a detector scan may be used to predict by interpolation the amount of signal contributed by photo-conductive induced offset for each row of the detector scan on a column by column basis.

Method and apparatus for correcting the offset induced by field effect transistor photo-conductive effects in a solid state x-ray detector

A low power CAM architecture is disclosed. Matchlines of the CAM array are sequential into a main search portion and a main search portion. After issuing a search command, a main search operation is conducted on the main search portion of the matchline. If the result of the main search is a match, then the main search is subsequently conducted on the main search portion of the matchline. If the result of main search is a mismatch, then the main search is disabled, and consequently there is no power dissipation on the main search portion of the matchlines. Main search and main search operations can be pipelined to maintain high throughput with minimum latency. Power consumption is further reduced by using a matchline sense circuit for detecting a current on the main search and main search portions of the matchline. Matchlines are decoupled from the sense circuit sense node in order to achieve higher sensing speed and improved sense margins, and dummy matchlines are used to generate timed control signals for latching the output of the matchline sense circuits. The matchlines are initially precharged to a miss condition represented by ground potential and are then undergo accelerated precharge to a preset voltage potential level below VDD to overcome tail-out parasitic current and to minimize the voltage swing of the matchlines to conserve power.

Low power content addressable memory architecture

A technique is provided for increasing the pixel pitch without increasing the interconnect density of a digital detector. Generally, a digital detector has an array of rows and columns of pixels, read out electronics and scan electronics, that are configured to generate and transmit signals based upon radiation impacting the detector. The detector also having a plurality of scan lines, which are coupled to the plurality of rows of pixels. The present technique also provides a multiplexing circuit for selectively coupling the rows of pixels to the respective scan lines for read out of the signals.

Growing community of inventors

Ottawa, Canada

Douglas I Perry