International Business Machines Corporation

Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Douglas Hooker Bradley

Tai Anh Cao

Robert Alan Philhower

Sang Hoo Dhong

Brian King Flachs

Jonathan James DeMent

Gilles Gervais

Owen Chiang

Yoichi Nishino

Sherman Matthew Dance

Wai Yin Wong

A multiplier engine that reduces the size of the circuitry used to provide the multiplier engine, as well as increases the speed at which the multiplication algorithm is performed, are provided. The illustrative embodiments may comprise a M*8 multiplication engine having one or more 4:2 compressors that comprise only two full adders, as opposed to the three full adders in the known 5:2 compressor based architecture. The 4:2 compressors are able to achieve the same operation as the known 5:2 compressor based architecture by virtue of using the unused bits in a least significant portion of the partial product inputs to store the negate bit values. Moreover, a negate bit value that is not fused with the partial product inputs may be input to the 4:2 compressors for a bitposition.

Multiplier engine

A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

System and method for sorting processors based on thermal design point

An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

Circuit suitable for use in a carry lookahead adder

An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both &ldquo;on&rdquo; at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology

The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Conditional carry encoding for carry select adder

A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate. In one embodiment, the first stage, second stage, carry circuit, and sum circuit are comprised primarily of such transmission gates to the exclusion of conventional CMOS complementary passgate logic.

4:2 compressor circuit for use in an arithmetic unit

A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as program &ldquo;states&rdquo; with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process. The method keeps unconditional outputs of program states and updates conditional outputs and the program states execute until the VLSI design and verification is completed.

VLSI layout design jobs scheduling method

A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Growing community of inventors

Austin, TX, United States of America

Douglas Hooker Bradley