Motorola Corporation

Motorola Solutions, Inc.

Douglas H Weisman

David E Bockelman

Edgar Herbert Callaway, Jr

Gilberto Jacinto Hernandez

Robert E Stengel

Randy L Ekl

Thomas J Swirbel

David P Gurney

Lawrence N Dworsky

John K Arledge

Raymond Louis Barrett

Kenneth David Cornett

Wayne W Chiou

E S Ramakrishnan

George W Marlin

Ronald C Alford

Loi Q Ninh

Wayne Wen-Haw Chiou

A cognitive radio (CR) system () includes CR units () that determine and update location-based system operating parameters to avoid interference with other systems operating in the same frequency band. Operational Location Uncertainty region and Allowed Location Error regions can be applied. The CR unit trades off between both, available channels and maximum system operating parameters, such that as Location Uncertainty of the CR device increases, available CR channels and location-based CR system operating parameters decrease over a maximum network reach.

Method for addressing user location errors in a cognitive radio system

A method and apparatus for a highpass filter structure using transmission line construction which has multiple output tabs for selection of corner frequencies utilizing a plurality of resonators coupled to the transmission line. The transmission line has a characteristic impedance which increases exponentially with respect to a distance from the input.

Method and apparatus for a communications filter

A transmission line ( ) is formed to have a characteristic impedance which increases at a first substantially exponential rate with respect to a distance from the input ( ). A plurality of resonators ( ) are coupled to the transmission line and positioned at a plurality of locations along the transmission line. The plurality of resonators has resonant frequencies that decrease at a second substantially exponential rate with respect to the distance from the input. An output signal ( ) is obtained at a point in the filter that produces a filter response having a corner frequency.

Method and apparatus for creating a radio frequency filter

A method of interconnecting electrical terminations (,) of an integrated circuit die (,) to corresponding circuit traces (,) of a circuit carrying substrate (,). The die is placed in a cavity (,) in the substrate such that the electrical terminations on the die are aligned with corresponding circuit traces on the substrate, and so that the surfaces of the die and substrate are coplanar. A film (,) is vacuum laminated over the substrate and the die with heat and pressure. The film is then heated so that it flows to fill the spaces (,) between the die and sidewalls of the cavity, and is then cured. Excess film is then removed everywhere except that which is in the space between the die and the cavity walls. Electrical interconnections (,) are then plated up between the terminations and the circuit traces to bridge the distance between the terminations and the circuit traces. These interconnections are plated directly on the surface of those portions of the laminated film that lie between the sides of the die and of the cavity.

Method of interconnecting an embedded integrated circuit

A method of forming high resolution circuit features on a substrate. A `seed` layer of copper (110) is deposited on a dielectric substrate (100). A dielectric layer (120) is then deposited on the copper layer, and an aluminum `mask` layer (130) is deposited on the dielectric layer. A photoresist layer (140) is spun on or laminated to the aluminum. The photoresist layer is imaged and developed to define a circuit pattern such that portions (230) of the aluminum `mask` layer are revealed, and these revealed portions are further etched so as to reveal portions (320) of the dielectric layer that are directly underneath. The remaining portions of the photoresist layer are stripped away, along with the revealed underlying portions of the dielectric film, exposing portions (410) of the copper layer in the image of the circuit pattern. The remaining portions of the aluminum mask are then removed, and the exposed copper is then electroplated to form the desired circuit traces (600). The remaining portions of the dielectric layer are stripped to expose the unplated portions of the copper layer, and these unplated portions are etched away with acid.

Process for forming high aspect ratio circuit features

A three-dimensional inductor coil is fabricated on top of a semiconductor substrate. The fabrication process includes the steps of depositing a first photoresist layer (406), forming a trench therein, and filling the trench with electroplated metal (404). A second photoresist layer (408) is deposited, and first and second trenches (410) are formed therein and filled with electroplated metal (412). A third photoresist layer (416) is deposited and a trench (418) formed therein, and then filled with electroplated metal (420). The first, second, and third photoresist layers (406, 408, 416) are then removed to expose a multi-loop inductor coil (500, 550).

Method of forming a three-dimensional integrated inductor

An integrated inductor-capacitor (L-C) structure can be formed on a semiconducting substrate (10) by depositing a metal layer in a pattern that contains an inductor coil (14) and a capacitor bottom electrode (12). A CuFe.sub.2 O.sub.4 film (16) is then deposited on the substrate and over the metal pattern to form the dielectric portion of the L-C structure. A via (17) created in the CuFe.sub.2 O.sub.4 film exposes a portion of the inductor coil. Another metal layer (18) is then deposited over the CuFe.sub.2 O.sub.4 film and in the via, such that this metal layer is electrically connected to the inductor coil through the via. A pattern is also made in the second metal layer to form a top electrode (19) for the capacitor, over the corresponding capacitor bottom electrode, and to form a circuit interconnect to the inductor coil through the via.

Integrated inductor and capacitor on a substrate and method for

One method for fabricating solderable pads (406) onto a substrate (220) for direct chip attachment uses a multilayer metallization coating (500). The coating has a bottom layer (202) of indium-tin oxide, with an intermediate layer (204) of copper and a top layer (206) of indium-tin oxide. A masking layer (208) is deposited on the active display area (402) of the substrate, leaving the bonding pads uncovered. The revealed bonding pads are then plasma etched, using the polyimide as an etch resist, and the top layer of ITO is selectively removed to reveal the underlying copper layer. The exposed copper layer (204) is then plated with a solderable metal to the desired thickness to form bonding pads that may be used with direct chip attachment schemes.

Method for fabricating metallization patterns on an electronic substrate

A radio frequency electrical connection (600) between a pair of electrical devices is formed by a pair of uninsulated bond wires (601, 603). The uninsulated bond wires (601, 603) are twisted in a manner such that the wires form a twisted pair but do not physically touch each other over the length of the twisted section.

Spatially separated uninsulated twisted wire pair

A radio frequency electrical connection between a pair of electrical devices (101, 104) is formed by a pair of bond wires (102, 103) crossing (401) each other.

Twisted-pair wire bond and method thereof

A twisted-pair conductor line structure is formed on a substrate (22) having insulated conductive layers (10, 11). The conductive layers are used to form first, second, third, and fourth conductive planar segments (16). A first conductive link (17) joins the first and second planar conductive segments to provide a first signal path. Similarly, a second conductive link (17) joins the third and fourth planar conductive segments to provide a second signal path. The first and second conductive links are operatively arranged to form a twist (17)in the first and second signal paths, such that the resulting magnetic fields (57, 59) around the twisted conductive segments will be opposite to each other for cancelling each other out, in order to reduce the magnetic field radiation to the surrounding environment.

Horizontally twisted-pair planar conductor line structure

A method for adjusting the frequency of a piezoelectic resonator such as a quartz crystal is disclosed. The resonator is placed within its enclosure facing a metallic surface. The atmosphere within the enclosure is made suitable for supporting a glow discharge. An electrical potential is then established between the resonator electrode and the metallic surface causing mass to sputter between the electrode and to the metallic surface to vary the characteristics of the resonator.

Growing community of inventors

Sunrise, FL, United States of America

Douglas H Weisman