Nvidia Corporation

Other

Douglas H Rogers

Henry Packard Moreton

Walter E Donovan

Gary C King

Justin S Legakis

Paolo Enrique Sabella

Hassane S Azar

Duncan Andrew Riach

Shaun Ho

Kevin Allen Bjorke

William Orville Ramey, Ii

Douglas Sim Dietrich, Jr

Embodiments use hierarchical continuous level of detail (H-CLOD) trees with inherited splitting plane partitioning to reduce visual artifacts in renderings. For example, a three-dimensional mesh can be iteratively split, according to iteratively defined splitting planes, until sub-meshes are smaller than a predetermined bucket size. Each splitting can define a hierarchical level of a tree, so that the original mesh is a root node, each split sub-mesh is a child node, and the smallest meshes are leaf nodes. An H-CLOD tree can be generated by simplifying and combining each group of sibling node sub-meshes bottom-up into a simplified parent mesh accounting for inherited splitting planes, so that the tree has a most simplified mesh as its root node and a most un-simplified mesh formed by a combination of its leaf nodes. At render time, traversing the H-CLOD tree can produce a desired level of detail from the pre-computed nodes.

Hierarchical continuous level of detail for three-dimensional meshes

A fishing rod holder having a spring base, rod receiver, at least one rod receiver arm and a first spring. The spring base being mountable to a secure mount. The rod receiver including a top and bottom, and an open area within the rod receiver at the top to receive a fishing rod. The at least one rod receiver arm connecting the rod receiver to the spring base, wherein the rod receiver is connected by the at least one rod receiver to the spring base such that the rod receiver can pivot to provide motion during fishing. The first spring mounted between the spring base and the rod receiver to provide resistance to movement of the rod receiver.

Fishing rod holder with fishing motion capability

Methods and systems for decompressing data are described. The relative magnitudes of a first value and a second value are compared. The first value and the second value represent respective endpoints of a range of values. The first value and the second value each have N bits of precision. Either the first or second value is selected, based on the result of the comparison. The selected value is scaled to produce a third value having N+1 bits of precision. A specified bit value is appended as the least significant bit of the other (non-selected) value to produce a fourth value having N+1 bits of precision.

Data decompression with extra precision

Embodiments provide texture compression with high compression ratios and low decompression times. Some embodiments partition a texture map into texel blocks. The number of blocks is reduced until a compression threshold is reached, and the resulting blocks are stored as a codebook. An index array is generated by associating each texel block with an index and associating each index with the block in the codebook identified as a closest match to the associated texel block. The codebook may then be compressed according to a technique compatible with a GPU. In certain embodiments, to render a scene, a CPU 'inflates' the texture map by copying the appropriate codebook block to each indexed block location of the texture map, as defined by the index array. Because the codebook blocks are already compressed in a format compatible with the GPU, the inflated texture map is also compatible with the GPU without further processing.

High-compression texture mapping

The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.

Utilization of symmetrical properties in rendering

Methods and systems for compressing and decompressing data are described. A first value of N+1 bits and a second value of N+1 bits are reduced to strings of N bits each. The first and second strings of N bits are stored in a particular order relative to one another in a compression block. The particular order in which the first and second strings of N bits are stored in the compression block is used to derive a bit value that is then used in combination with one of the strings of N bits to reconstruct that string as N+1 bits.

Two component texture map compression

Discontinuities along texture mapped seams of three-dimensional models may be reduced by creating and sampling texture data outside of chart boundaries. When a texel center is not within a chart boundary (a group of connected triangles in texture space) a phantom face is generated that includes the texel center. Phantom texture coordinates are created for each texel center that is covered by the phantom face. The phantom texture coordinates are used to read a texture sample from another chart in texture space that is adjacent to the chart boundary in model space, producing a smooth transition across the seam.

Creating texture data outside of a chart boundary

An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

Integrated tessellator in a graphics processing unit

A system, method and computer program product are provided for improving image quality in a graphics pipeline. Initially, a difference is detected between a first pixel of a first frame to be outputted and a corresponding second pixel of a second frame outputted before the first frame. Such difference may be representative of motion which is capable of reducing image quality. A pixel output is then modified if such a difference is detected. This is accomplished utilizing texturing hardware in the graphics pipeline. Thereafter, the pixel output is outputted via a progressive or interlaced display system.

Method for improving quality in graphics pipelines through a frame's top and bottom field processing with conditional thresholding and weighting techniques

A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

Tessellation system, method and computer program product with interior and surrounding meshes

System, method and article of manufacture for fractional tessellation during graphics processing

A graphics accelerator pipeline including a rasterizer stage, a texture stage, and a combiner stage capable of producing realistic output images by mapping irregular textures to surfaces.

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Sunnyvale, CA, United States of America

Douglas H Rogers