Lattice Semiconductor Corporation

Douglas H Bower

Gregg R Josephson

David L Tennant

A single poly EE cell and an array using said cell, with the array being provided electrical connections such that the select gate for the read select transistor and the select gate for the write select transistor may be separately controlled. In the array, first level metal is utilized for connection to the gates of the read and write select transistors and second level metal is utilized for connection to the product term connections of the cell.

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Beaverton, OR, United States of America

Douglas H Bower