Micron Technology Incorporated

Douglas Eugene Majerus

Scott Anthony Stoller

Qisong Lin

Brent Byron

Steven J Hanna

A method includes determining, by component of a memory sub-system, workload characteristics corresponding to a workload to be received by the memory sub-system. The method can further include dynamically altering a performance attribute of the memory sub-system based, at least in part, based on the determined workload characteristics.

Memory sub-system performance shaping including controlling data traffic

Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.

Software instruction set update of memory die using page buffers

A variety of applications can include devices or methods that provide read processing of data in memory cells of a memory device without predetermined read levels for the memory cells identified. A read process is provided to vary a selected access line gate voltage over time, creating a time-variate sequence where memory cell turn-on correlates with programmed threshold voltage. Total string current of data lines of a group of strings of memory cells of the memory device can be monitored during a read operation of selected memory cells of the strings to which a ramp voltage with positive slope is applied to an access line coupled to the selected memory cells. Selected values of the change of the total current with respect to time, from the monitoring of the total current, are determined. Read points to capture data are based on the determined selected values. Additional devices, systems, and methods are discussed.

Continuous sensing to determine read points

A target value of programmed bits of a first programming distribution of a set of programming distributions associated with a memory device is established. A first read voltage level is applied to a wordline portion of the memory device. A count of programmed bits in the set of programming distributions corresponding to the first read voltage level is determined. A measured ratio of the programmed bits of the first programming distribution to the count of programmed bits in the set of programming distributions is determined. The target value is compared to the measured ratio to determine a comparison result. An action is executed in view of the comparison result.

Adjusting read voltage levels based on a programmed bit count in a memory sub-system

Memory sub-system performance shaping including adding a delay to particular data traffic

A target value of programmed bits is established for each programming distribution of a set of programming distributions of a memory sub-system. A read voltage level is applied to determine a measured value of programmed bits in one or more programming distributions of the set of programming distributions. The target value of programmed bits is compared to the measured value of programmed bits to determine a comparison result and an action is executed in view of the comparison result.

Described herein is a system that includes a memory component and a processing device coupled to the memory component. The processing device identifies, in a test mode, a memory location of a memory component that is available to write test data, and detects a loss of power to the system while in the test mode. Responsive to detection of the loss of power, the processing device performs a continuous sequence of write operations to write the test data to the memory location using holdup energy until an amount of holdup energy is expended. After reboot of the system, the processing device determines a number of write operations successfully completed in the memory location by the continuous sequence of write operations before the amount of holdup energy is expended, and determines whether the number of write operations successfully completed satisfies a defect criterion. Responsive to the number of write operations successfully completed satisfying the defect criterion, the processing device reports a defect associated with the holdup energy.

Holdup self-tests for power loss operations on memory systems

A variety of applications can include devices or methods that provide read processing of data in memory cells of a memory de vice without predetermined read levels for the memory cells identified. A read process is provided to vary a selected access line gate voltage over time, creating a time-variate sequence where memory cell turn-on correlates with programmed threshold voltage. Total string current of data lines of a group of strings of memory cells of the memory device can be monitored during a read operation of selected memory cells of the strings to which a ramp voltage with positive slope is applied to an access line coupled to the selected memory cells. Selected values of the change of the total current with respect to time, from the monitoring of the total current, are determined. Read points to capture data are based on the determined selected values. Additional devices, systems, and methods are discussed.

Described herein are embodiments related to holdup self-tests in memory sub-systems for power loss operations. A processing device receives a request to perform a holdup self-test to detect a defect in a holdup circuit that powers the processing device and a memory component in the event of power loss. The processing device identifies a memory location of memory that is available and, responsive to detection of a loss of power, performs a continuous sequence of write operations to the memory location using holdup energy until all of the holdup energy is expended. After reboot, the processing device determines a number of the write operations that were successfully completed in the memory location before all of the holdup energy was expended. The processing device determines whether the number satisfies a defect criterion. Responsive to the responsive to the number satisfying the defect criterion, the processing device reports the defect associated with the holdup circuit.

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Boise, ID, United States of America

Douglas Eugene Majerus