Dell Products Inc.

Dell USA L P

Advanced Micro Devices Corporation

Alcon Laboratories, Inc.

Douglas Elmer Wallace, Jr

James Bryce Mobley

Keith Alan Lyszkowski

Stephanus Saputro

Abeye Teshome

Christopher C Jung

Steven J Lash

Jonathan P Dowling

A technique for performing signal integrity analysis of a system includes providing a stimulus pattern and a model of the system and performing analog simulation of the model utilizing the stimulus pattern. The stimulus pattern includes sequences of signal transitions with associated transition times and the sequences of signal transitions conform to a bus protocol and the associated transition times are according to characteristics of the system. The stimulus pattern is generated by initializing each of the sequences of signal transitions to an initial signal value and the associated transition times to an initial time, generating subsequent signal values and subsequent transition times by applying protocol rules and calculating timing adjustments for each of a list of transactions; the subsequent signal values and subsequent transition times to be added to the sequences of signal transitions.

Programmable pattern generation for dynamic bus signal integrity analysis

A computer system includes a printed circuit board manufactured in accordance with simulated trace impedances and topologies. The printed circuit board includes trace impedances characterizing at least three dimensions of a multi-dimensional space of the printed circuit board. The printed circuit board design includes trace impedances and topologies obtained with the use of a quasi-Monte Carlo simulation methodology.

Computer system and printed circuit board manufactured in accordance with a quasi-Monte Carlo simulation technique for multi-dimensional spaces

In electronic equipment, such as, for example, a personal computer printed circuit board, an arrangement for mitigating EMI, noise and other spurious signals at high frequencies. The arrangement includes a discrete capacitor coupled between an active pad and a reference pad. A conductor is coupled to the discrete capacitor and is configured to include a serpentine trace and a terminating tuning capacitance that are effectively series resonant at a predetermined frequency. In an exemplary embodiment, the serpentine trace comprises a number of substantially linear, mutually parallel segments that are joined by turns. The length and width of the serpentine trace, together with the number and spacing of linear segments, cooperates with the geometry of the tuning capacitance to determine the frequency of maximum attenuation of spurious signals.

Printed circuit suppression of high-frequency spurious signals

A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

Ground bounce detection circuit for use in data error reduction

A data processing system having mismatched impedance components and method of use is disclosed. In one embodiment, the method includes exciting a printed circuit board circuit having mismatched impedance printed circuit board components. Measuring at least one impedance of the circuit with a time domain reflectometer. In response to the measured at least one impedance of the circuit, adjusting at least one printed circuit board circuit element.

Data processing systems having mismatched impedance components

A methodology for predicting incidents of ground bounce and using this information for reducing data error caused thereby is described. In one embodiment, data to be clocked into a plurality of output buffers from a first register is read before it goes to the buffers and a determination is made as to what number of bits B will change state, i.e., from a zero to a one or a one to a zero. B is then compared to a predetermined threshold T. If B is greater than T, a wait state or some other indication is issued when the bits are clocked into the I/O buffers.

Ground bounce prediction methodology and use of same in data error reduction

A technique for reducing such ground bounce using phased outputs and package de-skewing for source synchronous buses is described. In one embodiment, the output buffers of an integrated circuit (&ldquo;IC&rdquo;) are phased so that half of the buffer outputs are driven first and the remaining half are driven a slight time delay later. The outputs are then de-skewed by package routing so that the earlier signals reach the package pins at the same time as the later signals. This deskewing is accomplished by serpentining and length-matching the bank of non-delayed outputs so that these trace-induced delays match an optimized fixed clock delay used to delay the bank of delayed outputs, the traces of which are length-matched and routed as short as possible.

Ground bounce reduction technique using phased outputs and package de-skewing for synchronous buses

A thermal management of a computer system may be advantageously obtained by predicting temperature variations based upon past temperature readings. Such a system may, in preferred embodiments, filter the past temperature data to provide a more precise value, allow for a floating trip level that will change with the rate of temperature change and even allow for prediction of the amount of time left before a system shutdown may occur.

Thermal management data prediction system

A multiple fan system including at least two simultaneously operated fans. Each of the fans are operable as a constant speed fan and as an oscillating speed fan. Not more than one of the fans is operated as a constant speed fan. Each fan not being operated as a constant speed fan is operated as an oscillating speed fan. A fan controller operates each oscillating speed fan in a mode whereby a respective acoustic emission having a range of frequency different than any other oscillating speed fans is produced.

Multiple fan system having means for reducing beat frequency oscillations

Multiple fan having means for reducing beat frequency oscillations

A multi-layer circuit substrate having an integral bus portion includes a dielectric substrate having a first device signal layer formed on a first side thereof and a second device signal layer formed on a second side thereof. The first and second device signal layers are each patterned to include at least one bus reference plane. A device reference plane layer is disposed between the first and second device signal layers in the dielectric substrate. The device reference plane layer is patterned to include a plurality of guard bands and a bus signal trace between at least two of the guard bands.

Controlled impedance bus and method for a computer system

A process control system according to the present invention uses analog control circuitry in which a differential amplifier stage is incorporated into the feedback path rather that the feedforward path to enable the control of highly non-linear processes that may also exhibit high levels of hysteresis. Such processes often have superior performance characteristics that conventional control circuitry cannot exploit. The present invention additionally incorporates an automatic control circuit which varies the gain of various stages the control circuitry when the output of the process is within a predetermined range. An embodiment of the present invention is used to control a nonlinear proportional valve with severe hysteresis. The valve regulates the pressure within pressure-driven ophthalmic surgical instruments, which must be controlled extremely precisely to enable successful eye surgery.

Growing community of inventors

Austin, TX, United States of America

Douglas Elmer Wallace, Jr