International Business Machines Corporation

Douglas Ele Martin

Christopher McCall Durham

Harsh D Sharma

Visweswara Rao Kodali

Daniel Mark Dreps

Michael J Lee

A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.

Domino to static circuit technique

A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode of this PFET also receives the data signal to be driven. A plurality of these driver circuits may be connected in parallel and in series in order to modify the output impedance.

Driver circuit having reduced noise

A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.

Reduced power dynamic logic circuit that inhibits reevaluation of stable

A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

Method and apparatus with preconditioning for shifting the voltage level

The invention is embodied in a receiver and a method for responding to an input signal. The input signal is received in a first stage of the receiver, which generates a first stage output signal responsive thereto. If the input signal does not exceed a first level, the first stage output signal is generated by an overvoltage element. That is, for this case, the overvoltage element passes the input signal through to the first stage output, and the first stage output voltage is not increased by a first stage pullup element. If, on the other hand, the input signal exceeds the first level, the first stage output signal voltage level is increased by the first stage pullup element to a higher output voltage level. The output signal from the first stage is received in a second stage. The second stage generates a second stage output responsive thereto. A second stage pullup element may be disabled by a mode signal in expectation that the input signal will exceed the first level, so that the first stage output voltage will not be increased by the second stage pullup element.

Method and apparatus for multi-level input voltage receiver circuit

A method and apparatus is disclosed for outputting a signal responsive to, and shifted in signal level relative to, an input signal level. A driver includes first circuitry outputting a first signal responsive to an input signal, and second circuitry outputting a second signal responsive to the input signal. The first circuitry includes circuitry for substantially shifting the first signal level relative to the input signal and responds more slowly than the second circuitry. The driver output is responsive to both the first and second signals so that the second circuitry improves driver response.

Method and apparatus with dual circuitry for shifting the level of a

In a method and apparatus for shifting the level of a signal a shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to changes in logic state of input signal and whose voltage level is shifted with respect to the input signal. The logic low state of the output signal is shifted to a certain voltage level above ground. A first switching device sets the voltage level of the logic low state. A feedback circuit feeds a signal derived from the output signal back to the switching device to precondition the shifter so that the speed of the output signal transition from one state to another is accelerated.

Method and apparatus with active feedback for shifting the voltage level

A memory system for providing a contiguous address space and including several memory modules each having circuitry to provide information of their respective memory module capacity to a control circuit. The control circuit allocates a start address to the first memory module and allocates start addresses to the remaining memory modules in accordance with previously allocated start addresses and the memory capacities of the memories that have received their respected start addresses. In one embodiment, the control circuit includes a series of adders each connected to a memory module to receive memory capacity data. The adders are connected in series to compute the start addresses in a daisy chain fashion.

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Round Rock, TX, United States of America

Douglas Ele Martin