Ncr Corporation

Teradata Us, Inc.

Tarari, Inc.

Lsi Corporation

Douglas Edward Hundley

P Keith Muller

Gene Robert Erickson

Curtis Hall Stehley

Robert J McMillen

Gregory Howard Milby

Gary Lee Boggs

Robert Samuel Cooper

Donald G Tipon

Eric T Lemoine

A data store system may include a storage device configured to store a plurality of data store tables. The data store system a further include a processor in communication with the storage device. The processor may receive a request to encode a column of a data store table from the plurality of data store tables. The processor may further generate a bit value representation of each value in the column of the data store table. The processor may further generate an index. The index may include an index value representative of each bit position of the bit value representations. The processor may further reorder bits of each bit value representation according to a predetermined pattern. The processor may further encode each reordered bit value representation according to an encoding technique. The processor may further store each encoded reordered bit value representations and the index. A method and computer-readable medium are also disclosed.

Bit reordering compression

A self-organizing list machine is provided for reordering items of a list in a manner that achieves both a constant and minimum time complexity. The self-organizing list machine comprises an array of symbol index generators, wherein (i) each symbol index generator has a unique location in the array between zero and N&#x2212;1 inclusive, and (ii) N is the total number of unique symbols in a symbol alphabet.

Self organizing list machine for reordering items of a list

Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Hardware device comprising multiple accelerators for performing multiple independent hardware acceleration operations

Devices for performing multiple independent hardware acceleration operations and methods for performing same

A system for tokenizing a document, such as, for example, an XML document. A classifier is configured to assign the at least one character to at least one of a plurality of character classes. Each of a plurality of token logic units is configured to concurrently perform a comparison as specified by an instruction. A comparison may comprise comparing the at least one character class to an operand. An execution unit is configured to select an action from the instruction in response to performing the comparisons and to perform the action. A method of tokenizing a document includes assigning at least one character from a document to at least one of a plurality of character classes and concurrently performing a plurality of comparisons. At least one of the plurality of comparisons comprises comparing the assigned character class to the character from the document. At least one action to be performed is selected based on at least one result produced by performing the comparisons, and the selected action is subsequently performed.

System and method for tokening documents

An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.

ATM/SONET network enhanced as a universal computer system interconnect

A method of controlling an input/output (I/O) device connected to a computer to facilitate fast I/O data transfers. An address space for the I/O device is created in the virtual memory of the computer, wherein the address space comprises virtual registers that are used to directly control the I/O device. In essence, control registers and/or memory of the I/O device are mapped into the virtual address space, and the virtual address space is backed by control registers and/or memory on the I/O device. Thereafter, the I/O device detects writes to the address space. As a result, a pre-defined sequence of actions can be triggered in the I/O device by programming specified values into the data written into the mapped virtual address space.

Growing community of inventors

Poway, CA, United States of America

Douglas Edward Hundley