Digital Equipment Corporation

Lsi Corporation

Other

Douglas E Sanders

Michael A Callander

James W Keeley

Andrew Hyonil Chong

Linda Chao

Richard Lee Sites

William Ralph Wheeler

Derrick R Meyer

Nicholas D Wade

Raymond L Strouble

Rebecca L Stamm

G Michael Uhler

George M Uhler

John F Brown, Iii

William C Madden

Suparna Behera

Gordon Douglas Boyd

Ju-Ching Tang

Richard John Bombard

Daniel W Meyer

Jeffrey William Breti

Philip Waldron Herman, Jr

R Iris Bahar

Harish Bharadwaj

Soha M Hassoun

Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.

Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system

Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.

Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop

A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver. The CCE is operated to selectively process the credit count information stored in the repository, in order to generate an update credit count. The update credit count is then selectively sent to a given Transmitter, to enable the given Transmitter to send a transmission to the given Receiver.

Method and apparatus for managing flow control in PCI express transaction layer

A new prefabricated door frame assembly for ready on site adaptation and attachment to a structure. The inventive device includes an inner door frame, for mounting a door thereon, surrounded by an outer framing frame, for attachment to a structure, with a pair of side glass panels each shaped to fit between the sides of the door frame and the framing frame, and a transom glass panel between the top of the door frame and the framing frame.

Prefabricated door frame assembly

A parity generator for multibit binary data in which only a subset of bits change at one time includes a circuit for determining whether the number of bits in the subset to be changed is odd or even. A toggle signal generator generates a toggle signal only if the number of bits to be changed is odd. A toggling circuit selectively changes the level of the parity bit in response to the toggle signal.

Method and apparatus for parity generation

A CPU module has a processor, cache memory, cache controller, and system interface attached to a processor bus. The system interface is attached to a system bus shared by memory, I/O, and other CPU modules. The cache controller requests control of the processor bus from the processor, and grants control to the system interface. The system interface uses the processor bus to store fill data obtained from memory into the cache in response to a read miss. The system interface also monitors system bus traffic and forwards the addresses of cache blocks to be invalidated to the cache controller over an invalidate bus. The cache controller requests control of the processor bus during a read miss to perform invalidates and writebacks. The processor grants control to the cache controller before the read miss completes, enabling the cache controller to proceed, and then re-issues the read. A protocol between the cache controller and the system interface ensures that cache fills, invalidates, and writebacks are done in the correct order to maintain data coherency. As part of this protocol, the cache controller decides when the system interface may proceed with a fill, and grants the processor bus to the system interface accordingly.

Method and apparatus for controlling a processor bus used by multiple

A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also includes an error detector for detecting an error in the tag store information. Circuitry is included for reporting an error and saving the index which caused the error if an error is detected but no error has been previously detected. Comparing circuitry is included for comparing the index causing the current error to the previously saved address if an error is detected and an error has been previously detected; and if the address is not the same, then reporting a fatal error; otherwise, if the index is the same, then not reporting a fatal error.

Apparatus for suppressing an error report from an address for which an

A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.

Two-level protocol for multi-component bus ownership, and implementation

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency. For CAL type instructions, a method for determining which registers need to be saved is executed in a minimum number of cycles, examining groups of register mask bits at one time. Internal processor registers are accessed with short (byte width) addresses instead of full physical addresses as used for memory and I/O references, but off-chip processor registers are memory-mapped and accessed by the same busses using the same controls as the memory and I/O. In a non-recoverable error detected by ECC circuits in the cache, an error transition mode is entered wherein the cache operates under limited access rules, allowing a maximum of access by the system for data blocks owned by the cache, but yet minimizing changes to the cache data so that diagnostics may be run. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.

Error transition mode for multi-processor system

To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with 'state silos' that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.

Application of state silos for recovery from memory management exceptions

A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.

Growing community of inventors

Framingham, MA, United States of America

Douglas E Sanders