Texas Instruments Corporation

Douglas E Mercer

Luigi Colombo

Antonio L P Rotondaro

Mark R Visokay

Noel M Russell

Peijun Chen

Rajesh B Khamankar

Doufeng Yue

Andrew Marshall

Haowen Bu

David Barry Scott

Rick L Wise

Malcolm John Bevan

Duofeng Yue

Youngmin Kim

Aditi D Banerjee

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Gate structure and method

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, germanium atoms () and transition metal atoms () to form a metal-germanium alloy layer () on a semiconductor substrate (). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

Metal-germanium physical vapor deposition for semiconductor device defect reduction

CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Gate dielectric and method

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, halogen atoms () and transition metal atoms () to form a halogen-containing metal layer () on a semiconductor substrate (). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit () comprising the metal silicide electrode.

Metal-halogen physical vapor deposition for semiconductor device defect reduction

Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

Method for integrating high-k dielectrics in transistor devices

A method of forming a semiconductor circuit ( ). The method forms a first transistor (NT ) using various steps, such as by forming a first source/drain region ( ) as a first doped region in a fixed relationship to a semiconductor substrate ( ) and forming a second source/drain region ( ) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate ( ) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST ) using various steps, such as by forming a third source/drain region ( ) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region ( ) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate ( ) in a fixed relationship to the third source/drain region and the fourth drain region. Also in the preferred embodiment method, the steps of forming the first gate and the second gate comprising forming the first gate to comprise a first dopant concentration and forming the second gate to comprise a second dopant concentration different from the first dopant concentration.

Memory cell with transistors having relatively high threshold voltages in response to selective gate doping

An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate, the method comprising the steps of: forming a doped polycrystalline silicon layer insulatively disposed over the semiconductor substrate; and subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds. Preferably, the oxidizing ambient is comprised of: O,,O,, NO, N,O, H,O, and any combination thereof. The temperature is, preferably, around 950 to 1050 C. (more preferably around 1000 C.). The step of subjecting the doped polycrystalline silicon layer to a temperature of around 700 to 1100 C. in an oxidizing ambient for a period of around 5 to 120 seconds, preferably, forms an oxide layer on the polycrystalline silicon layer, which has a thickness which is, preferably, greater than the thickness of a native oxide layer. More preferably, it has a thickness which is greater than 3 nm (more preferably greater than 2 nm). In an alternative embodiment, the thickness of the oxide layer is less than 20 nm (more preferably, less than 10 nm thick).

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Richardson, TX, United States of America

Douglas E Mercer