Harris Corporation

Douglas E Heckaman

Walter M Whybrew

Roger H Higman

Jeffrey A Frisco

Edward J Bajgrowicz

Jeffery C May

Gary A Rief

Gilbert Reeves Perkins

Gregory M Jandzio

Alan William Mast

John Warner Shipley

William Edward Clark

Brett A Pigon

James B Nichols

Randy Eugene Boozer

David B Kanaly

David A Haskins

Jerry B Schappacher

Dawn A Larson

John E Baker

Gregory C Rieder

Diane G Caruso

Robert J Schrimpf

Augusto E Rodriguez

Ronald Vought

An interconnect structure interconnects electronic modules and includes a backplane assembly formed from a substantially rigid backplane plate that carries RF connectors and a digital motherboard having digital connectors for mating with digital connectors of electronic modules. A controlled impedance interconnect circuit is positioned on the rear surface of the backplane plate and interconnects the RF connectors carried by the backplane plate and digital connectors of the digital motherboard. A rack receives the backplane assembly and supports a plurality of electronic modules that are interconnected to each other via the backplane assembly.

Interconnect structure for interconnecting electronic modules

A phased array antenna includes an antenna housing having an array face defining an electrically conductive ground plane layer. A plurality of millimeter wavelength patch antenna elements are positioned on the array face and each include a primary substrate having front and rear sides and a driven antenna element positioned on the front side of the primary substrate. A ground plane layer is positioned on the rear side of the primary substrate and a dielectric layer is positioned on the ground plane layer. A microstrip quadrature-to-circular polarization circuit is positioned on the dielectric layer. A parasitic antenna element layer is spaced forward from the driven antenna element and at least one spacer is positioned between the parasitic antenna element layer and the primary substrate. This spacer is dimensioned for enhanced parasitic antenna element performance at millimeter wavelength radio frequency signals.

Phased array antenna having patch antenna elements with enhanced parasitic antenna element performance at millimeter wavelength radio frequency signals

An antenna device includes a dual polarized quad-ridge antenna horn having an electrically conductive conduit with first and second opposite ends along a horn axis. Four electrically conductive ridges are carried on an inner side of the electrically conductive conduit. A printed wiring board including a dielectric substrate is connected across the first end of the dual polarized quad-ridge antenna horn and transversely to the horn axis. Furthermore, an electrically conductive pattern is formed on the dielectric substrate and defines feed elements for the dual polarized quad-ridge antenna horn.

Antenna horn and associated methods

A phased array antenna includes an antenna housing having a subarray assembly that supports beam forming network modules and an array face defining a ground plane substantially orthogonal to the subarray assembly. A plurality of millimeter wavelength patch antenna elements are positioned on the array face and each positioned adjacent a respective subarray assembly. The millimeter wavelength patch antenna elements each include a driven antenna element having a front and rear side and a parasitic antenna element positioned forward of the front side of the driven antenna element. A microstrip quadrature-to-circular polarization circuit is positioned rearward of the rear side of the driven antenna element and operatively connected to the driven antenna element. A single millimeter wavelength feed operatively connects the microstrip quadrature-to-circular polarization circuit with a respective adjacent beam forming network module supported on the orthogonal positioned subarray assembly.

Phased array antenna having stacked patch antenna element with single millimeter wavelength feed and microstrip quadrature-to-circular polarization circuit

A multi-tile configured, two-dimensional phased array antenna architecture is configured of an gridwork of sub-array `tiles`, each of which contains a mechanically integrated and RF-integrated antenna elements and RF interface components therefor. Each tile is formed of a multilayer printed wiring board and supports a sub-array of antenna elements and their associated RF circuits, so that the tile itself is effectively an operative phased-array antenna. The gridwork supports the sub-array tiles in sealed engagement with the framework, whereby associated RF networks components at rear sides of the tiles are protected against the free space environment to which the antenna elements on front faces of the tiles are exposed. Each RF interface network contains signal processing circuitry for controlling the operation of a respective one or a set of the antenna elements on the front side of the tile.

Multi title-configured phased array antenna architecture

A stripline cross-over architecture includes a first stripline layer extending on a first side of a dielectric layer between a first signal input port and a plurality of first signal output ports. A second stripline layer extends on a second side of the dielectric layer between a second signal input port and a plurality of second signal output ports, crossing over the first stripline layer at a plurality of cross-overs of mutual overlap therebetween. The electrical lengths of the stripline layers are defined and the cross-overs are located such that electrical distances between the cross-overs and signal combination locations cause cross-coupled signals to cancel one another, when non cross-coupled signals are combined in phase.

Cross-over distribution scheme for canceling mutually coupled signals

A distributed ground pad-based isolation arrangement for a multilayer stripline architecture is configured to effectively inhibit the mutual coupling of signals between overlapping regions of adjacent stripline networks of dielectrically separated transmission networks, without substantially increasing either the mass of the laminate structure or the lossiness of the stripline. At regions of mutual overlap, the stripline layers are spatially oriented at right angles to one another, and a limited area ground pad is interleaved between the stripline layers. To maintain the desired characteristic line impedance of a stripline layer as it passes over a ground pad, the width of the stripline layer is reduced in the overlap region. Each ground pad is connected to an external ground reference by plated vias, that extend through the dielectric layers and intersect outer grounded shielding layers of the laminate.

Distributed ground pads for shielding cross-overs of mutually

A stripline isolation cross-over is configured to cancel signals that may be mutually coupled at cross-over points between adjacent stripline networks within a compact multilayer signal distribution architecture, such as one feeding elements of phased array antennas, without a shielding layer between adjacent signal distribution networks. The signal distribution networks includes layers of stripline, patterned on opposite sides of a dielectric layer. Wherever the stripline layers mutually overlap, they are oriented at right angles to one another, and one of the striplines is configured as a pair of power dividers, connected back-to-back via stripline interconnect passing the other stripline layer, to form a signal splitting-recombining stripline pair. The locations where the sections of interconnect cross the second stripline are spaced apart by a half-wavelength of transported signals, so that any signal mutually coupled between the two striplines at each cross-over point will combine antiphase with itself, thereby effectively preventing mutual interference between the two networks.

High isolation cross-over for canceling mutually coupled signals between

A flat panel-configured electronically steered phased array antenna includes a planar distribution of densely nested microstrip dipole sub-arrays, arranged and controlled in a manner similar to microstrip `reflect-array` antenna elements. The resultant phase of a circularly polarized wave for a reflect-array fan-out distribution of dipole antenna elements is controlled by an associated plurality of triode-configured field emission devices. Each dipole element sub-array is plated to a resistive sub-layer on an interior surface of a flat first millimeter wave transmissive panel member of an evacuated flat panel type support structure. Mounted to a similar resistive layer on the interior surface of a second, flat panel member is a microstrip conductive layer partially overlapped around its periphery by respective fan-configured microstrip dipole antenna elements plated on the first panel member. Arranged between overlapping regions and overlapping portions of the respective dipole antenna elements are a plurality of elements, that form cathode and control gates of plural triode-configured field emission devices, the anodes of which are dipoles formed on the first plate member. These elements select a desired dipole pair within each subarray and control the current therein.

Flat panel-configured electronically steerable phased array antenna

A miniaturized cylindrical `channeline` delay line comprises a plurality of concentrically stacked cylindrical elements, surfaces of which are configured to form helically contoured `channeline` transmission line. The nested stack includes a first, generally cylindrical conductive spool body element, for example a lightweight and electrically conductive cylinder or spool, having a longitudinal axis and an outer, generally cylindrical surface in which a helical groove is formed. Concentrically surrounding this interior spool are one or more additional, generally cylindrical hollow electrically conductive hollow cylinders of successively increasing diameters. These additional electrically conductive hollow cylinders are sized, so that respective ones of the cylinders may be concentrically stacked about the longitudinal axis of the interior spool. Like the interior spool, each surrounding cylinder has a helical groove formed in its outer cylindrical surface. Snugly surrounding the outermost hollow cylinder is a conductive cylindrical cover for the structure, which has a generally cylindrical bore that is sized so as to accommodate the insertion of the interior spool and the concentrically stacked one or more cylindrical hollow cylinders into its bore. Respective lengths of insulator clad center conductor are wound within respective ones of the helical grooves in the interior spool and the cylinders, so as to be electrically insulated from the electrically conductive surfaces of respective ones of the helical grooves and the bores of adjacent body elements.

Compact delay line formed of concentrically stacked, helically grooved,

A high isolation broadband switching circuit includes a plurality of switching elements coupled in series alternatingly with transmission line segments. Each switching element has a low or very high impedance between first and second points responsive to first and second values of a control voltage, respectively. In a first embodiment, the switching element includes a PIN diode having a cathode coupled to a first transmission line and an anode coupled to a second transmission line. In a second embodiment, the switching element includes a field effect transistor (FET) having a drain coupled to a first transmission line and a source coupled to a second transmission line. A first resistor is coupled between the drain and the source for DC continuity between the drain and the source, and a second resistor coupled between a gate of the FET and ground for DC continuity. A bias voltage source is coupled through a resistor to one of a source and a drain of one of the FETs. A bias voltage propagates through each transmission line and each first resistor, so DC continuity is provided. The bias voltage has a first value which causes the switching elements to have a low impedance to place the switching circuit in an ON state, and a second value which causes the switching elements to have a high impedance to place the circuit in a non-conductive state. The high impedance of the switching elements effectively opens the connections between the transmission lines.

High isolation integrated switch circuit

Directed millimeter wave radiation from internal elements of a microwave circuit through the housing cover, housing base, and side walls of a hermetically-sealed MMIC integrated subsystem assembly uses a waffle-wall array of conductive posts as a band rejection filter to provide walls which guide the radiated waves through a hermetically sealed window in the housing base for waveguide propagation or to a dielectric side wall or cover to radiate energy therethrough. For a waveguide launch, the launch probe is printed on a TEM mode microstrip transmission line substrate and is located over or on a dielectric window formed at the end of an air filled waveguide. A waveguide-like mode of propagation is launched perpendicular to the microstrip substrate and the energy is transmitted through the dielectric window into the air dielectric waveguide which extends through the housing base. Side wall mounted antennas use radiating elements placed near the side walls of the subsystem assembly and are surrounded on their remaining sides by the conductive post structure. The launched waves propagate toward the dielectric side wall to radiate outwardly from the subsystem assembly. For radiating energy through the subsystem assembly cover, a launch probe is located under a dielectric aperture in the hermetically-sealed cover.

Hermetically sealed waffle-wall configured assembly including sidewall

A waffeline-configured, surface-mount transmission line module contains a two-dimensional arrangement of periodically distributed conductive surface mesas and channels. Within the channels are segments of dielectrically surrounded conductor. The geometry of the arrangement of segments among the waffleline channels is defined in accordance with the intended signal coupling functionality of the interconnect structure. For example, in the case of a signal splitting application, the conductor segments may be arranged in a tree-like configuration between an input port and multiple output ports. Isolation resistors may be disposed within the channels of the waffleline between adjacent locations of diverging conductor runs among the mesas of the waffleline. The resulting transmission line module is then surface-mounted on the same printed wiring board as the signal processing components it is to interconnect, and respective portions of the segments of dielectrically surrounded conductor within the channels of the waffleline module are connected to signal ports of adjacent signal processing components. Because each waffleline interconnect module is relatively thin, multiple modules may be mounted in a stacked configuration on the printed wiring board to realize a three-dimensional waffleline module structure, with intermodule vias and interconnects provided between selected locations of conductor segments of adjacent layers.

Waffleline-configured surface-mount package for high frequency signal

A packaging structure mounts integrated circuit chips in a nested, cavity-up configuration, so as to permit access to the modules for reworkability, but without the use of a separate printed circuit board for support and interconnect among the modules. Each monolithic integrated circuit module comprises a cavity-up leadless chip carrier which is affixed to its own dedicated thermally and electrically conductive mounting base, that effectively plugs into an underlying ground plane, heat sink support. The mounting base may comprise of a thin conductive plate having a cylindrical stem, through which the mounting base is retained within an aperture in the underlying support. The underlying support has a plurality of cylindrical stem engaging apertures distributed in a matrix configuration, so that the insertion of a plurality of chip carrier mounting bases into the apertures of the matrix causes the mounting bases to be aligned edgewise in a tight edge-to-edge array. Distributed along edge portions of a mounting base contact regions to which conductive traces from topside wirebond links on the chip extend. Interconnection between chip carriers may be accomplished by elastomeric connectors bridging the contact regions of the mutually aligned edges of the mounting bases. Circuit-to-circuit interconnections are accomplished through IC chip wiring layers or an additional wiring layer in the chip carrier.

Method of making a high speed, high density semiconductor memory package

A package for a microwave circuit chip and associated microstrip antenna is formed of a multi-layer ceramic laminate within which is supported a microwave chip carrier and on an outer surface of which a microstrip antenna disposed. A first ceramic layer is supported on metallic base member and contains signal lines for interfacing the chip with the external world. Disposed atop the first ceramic layer is a second ceramic layer which forms a protective seal ring around the perimeter of the chip. A third ceramic cover layer is mounted atop the seal ring layer and contains one or more antenna elements on its outer surface. Signal line connections between the chip and the antenna elements are effected through tuned networks that extend from signal leads on the chip to conductors on the first ceramic layer. Signal connections from the first ceramic layer to the antenna on the cover may be formed by conductive vias through the ceramic seal ring layer or conductors along sidewalls of the seal ring layer and cover. Preferably, the first layer and the seal ring layer contain a ground plane vias distributed around the perimeter of the chip, to provide electrical continuity between the metal base member and a ground plane on the interior surface of the cover.

Growing community of inventors

Indialantic, FL, United States of America

Douglas E Heckaman