Enpirion, Inc.

Agere Systems Inc.

Altera Corporation

Agere Systems Guardian Corp.

Lucent Technologies Inc.

At&t Bell Laboratories

Empirion, Inc.

Douglas D Lopata

Ashraf W Lotfi

John David Weld

Tanya Nigam

William W Troutman

Jeffrey Demski

Jay Norton

Mathew A Wilkowski

Anatoly Feygenson

Malcolm Harold Smith

Maarten Visee

Narciso Mera

Jan Amerom

Miguel Rojas-Gonzales

Guus Jansen

Marcel Slomp

Wei Zhang

Bernard Lee Morris

Richard Joseph McPartland

Roger A Fratti

Wayne E Werner

Thomas Baker

Dale Harvey Nelson

Hai Quang Pham

Paul C Davis

Lawrence Allen Rigge

Thayamkulangara R Viswanathan

Roger Anthony Fratti

Stanley Reinhold

Mark K Lesher

Trudy Dawn Stetzler

Owe George Petersen

Mathew R Henry

Gary Carlos Crain

Chaitanya Chava

John Thomas Falkowski

Bruce Godley Littlefield

Hussein K Mecklai

Miguel Rojas-Gonzalez

A circuit system includes a current sensor circuit, a subtractor circuit, a multiplier circuit, and a divider circuit. The current sensor circuit generates a current sense signal that indicates a current through an inductor. The circuit system generates a current value based on the current sense signal. The subtractor circuit determines a voltage difference across the inductor. The multiplier circuit multiplies the voltage difference by a time period that the voltage difference is applied across the inductor to generate a product. The divider circuit divides the product by the current value to generate an estimated inductance of the inductor.

Techniques for determining inductances

An integrated current replicator includes a first current sense resistor configured to sense a first input current to a power converter during a primary portion of a duty cycle and a first transconductance amplifier configured produce a first voltage at a common circuit node proportional to the first input current during the primary portion of the duty cycle. The integrated current replicator includes a second current sense resistor configured to sense a second input current to the power converter during a complementary portion of the duty cycle and a second transconductance amplifier configured produce a second voltage at the common circuit node proportional to the second input current during the complementary portion of the duty cycle. The integrated current replicator includes an amplifier configured to produce a voltage replicating the first input current and the second input current from the first voltage and the second voltage.

Integrated current replicator and method of operating the same

A semiconductor device having substantially minor-symmetric terminals and methods of forming the same. In one embodiment, the semiconductor device includes a semiconductor switch having a control node and a switched node, the switched node being coupled to first and second output terminals of the semiconductor device, the first and second output terminals being positioned in a substantially minor-symmetric arrangement on the semiconductor device. The semiconductor device also includes a control element having first and second input nodes and an output node, the first and second input nodes being coupled to first and second input terminals, respectively, of the semiconductor device and the output node being coupled to the control node of the semiconductor switch, the first and second input terminals being substantially center-positioned on the semiconductor device.

Semiconductor device having mirror-symmetric terminals and methods of forming the same

A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a power switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the power switch. The resistor metallic layer includes a current sense resistor including a first current sense resistor metallic strip coupled between a first cross member and a second cross member, and a first gain resistor including a first gain resistor metallic strip coupled to the first cross member. The semiconductor device also includes an amplifier over the substrate and coupled to the first gain resistor metallic strip.

Semiconductor device including a resistor metallic layer and method of forming the same

An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage.

Power converter for a memory module

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor ('LDMOS') cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

Semiconductor device including a redistribution layer and metallic pillars coupled thereto

A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.

A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor ('LDMOS') cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.

Semiconductor device including gate drivers around a periphery thereof

A semiconductor device and method of forming the same including, in one embodiment, a substrate and a plurality of source and drain regions formed as alternating pattern on the substrate. The semiconductor device also includes a plurality of gates formed over the substrate between and parallel to ones of the plurality of source and drain regions. The semiconductor device also includes a first plurality of alternating source and drain metallic strips formed in a first metallic layer above the substrate and parallel to and forming an electrical contact with respective ones of the plurality of source and drain regions.

Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips

A power converter and method of controlling the same for selected modes of operation. In one embodiment, the power converter includes a first power switch coupled to a source of electrical power and a second power switch coupled to the first power switch and to an output terminal of the power converter. The power converter also includes a controller configured to control an operation of the first and second power switches during selected modes of operation.

Power converter with controller operable in selected modes of operation

A module having a discrete passive element and a semiconductor device, and method of forming the same. In one embodiment, the module includes a patterned leadframe, a discrete passive element mounted on an upper surface of the leadframe, and a thermally conductive, electrically insulating material formed on an upper surface of the discrete passive element. The module also includes a semiconductor device bonded to an upper surface of the thermally conductive, electrically insulating material.

Module having a stacked passive element and method of forming the same

An integrated circuit with a transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the transistor includes a source/drain including a lightly or heavily doped region adjacent the channel region, and an oppositely doped well extending under the channel region and a portion of the lightly or heavily doped region of the source/drain. The transistor also includes a channel extension, within the oppositely doped well, under the channel region and extending under a portion of the lightly or heavily doped region of the source/drain.

Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same

Growing community of inventors

Boyertown, PA, United States of America

Douglas D Lopata