Lattice Semiconductor Corporation

Douglas C Morse

David Clark Wilkinson

Clement Lee

Jock F Tomlinson

James J Bennett

Hans W Klein

Edward W Miller

Edward A Ramsden

Frederic N F Deboes

Randall S Skinner

Power-sequencing controllers are connected to allow more complex power sequencing and/or larger numbers of voltage supplies to be monitored than with a single controller. Power-on-reset (POR) output signals from the 'slave' controllers are connected by a wired-OR, and the composite output is used as a reset signal or indicator signal by the 'master' controller. An output from the master controller coupled to the composite input signal is connected with the {overscore (POR)} output of the master controller by a wired-OR, and this composite signal is coupled to the reset terminals of the slave controllers. Connecting controllers in a master/slave configuration allows prevents any of the slave devices from starting until all the devices have been released, resulting in synchronous processing of subsequent signals and events.

Expansion method for complex power-sequencing applications

A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.

Programmable power management system and method

A method and apparatus is provided to power-up a device having both digital and analog circuitry. The analog circuitry requires a stabilization period before proper operation. During power-up, the digital circuitry is held in reset by a power-on reset circuit. The power-on reset circuit releases the reset after the expiration of a power-on reset period. During the period of time after expiration of the power-on reset period and before the analog circuitry reaches equilibrium, the digital circuitry operates in a mode that does not require input signals from the analog circuitry. After the analog circuitry has reached equilibrium, the digital circuitry begins normal operation during which inputs signals from the analog circuitry may be processed by the digital circuitry.

Powering-up a device having digital and analog circuitry

A voltage regulator module power supply, in accordance with an embodiment of the present invention, may be controlled by providing a modified voltage identification to the voltage regulator module power supply. The modified voltage identification may be utilized, for example, to apply margining and/or trimming techniques to the voltage regulator module power supply.

Systems and methods for controlling voltage regulator module power supplies

An input/output (I/O) circuit or cell associated with a pin of a programmable logic circuit allows the pin to be configured as for bidirectional input and output operations, without requiring a second one-bit register to be configured from the configurable logic elements of the programmable logic circuit. The I/O cell can be used in parallel-to-serial, serial-to-parallel and shift register operations.

Programmable input/output cell with bidirectional and shift register capabilities

A system receives a multiplexed input signal having a plurality of channels for data. The system includes a finite state machine which performs a predetermined logic operation on data in each of the channels of the multiplexed input signal. A memory, coupled to the finite state machine, stores at least one context of the finite state machine for each of the channels of the multiplexed input signal.

Finite state machine with associated memory

A method and a structure provide in a programmable logic device wide multiplexers without increasing delay and the number of interconnections in an input routing resource over corresponding multiplexer with less number of input signals. In one embodiment, each of a number of 8-input multiplexers shares both common input signals and common selection signals with a neighboring multiplexer. Even wider multiplexers can be achieved by cascading the multiplexers in a conventional manner.

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Yamhill, OR, United States of America

Douglas C Morse