Apple Inc.

Adaptec, Inc.

Douglas C Lee

Diarmuid P Ross

Tahoma Madrone Toelkes

John S Packer

David S Warren

Patrick D McNamara

Marc Spitzer

Alan R Gilchrist

Sung-Wook Kang

Craig A Pietrow

Fanyun (Michelle) Kong

In an embodiment, a peripheral component may include a low priority command queue configured to store a set of commands to perform a transfer on a peripheral interface and a high priority command queue configured to store a second set of commands to perform a transfer on the interface. The commands in the low priority queue may include indications which identify points at which the set of commands can be interrupted to perform the second set of commands. A control circuit may be coupled to the low priority command queue and may interrupt the processing of the commands from the low priority queue responsive to the indications, and may process commands from the high priority command queue.

High priority command queue for peripheral component

In an embodiment, a peripheral component may include multiple sources of commands, such as command queues and/or macro memories. The commands may be performed in the peripheral component and may result in an error. The peripheral component may include a trace queue into which the commands may be written, independent of the source of the commands. Thus, the trace queue may provide a record of recently performed commands.

Trace queue for peripheral component

A method and apparatus for scaling a DLL code for a slave DLL operating at a different frequency than a master DLL is disclosed. An apparatus includes a master DLL coupled to receive a first clock signal and a group of series-coupled slave DLLs coupled to receive a second clock signal. The master DLL may provide a specified fraction of a cycle of the first clock signal. Scaling circuitry coupled between the master DLL and the group of slave DLLs may determine a ratio of frequencies of the first clock signal to the second clock signal. Based on the ratio and a delay code from the first DLL, the scaling circuitry may generate an adjusted delay code received by the group of slave DLLs to set a delay for the second clock signal to the specified fraction.

Method and apparatus to automatically scale DLL code for use with slave DLL operating at a different frequency than a master DLL

A method and apparatus for training a DLL in a memory subsystem is disclosed. In one embodiment, a memory subsystem includes a memory coupled to convey data read therefrom on one or more channels. Each memory channel may include a delay locked loop (DLL) configured to apply a desired amount of delay to a data strobe signal received from the memory during a read operation. Upon detecting a read request, a controller may initiate a training procedure in which the DLL is trained to the desired delay. During the training procedure, an input clock signal may be provided to the DLL. The delay within the DLL may be adjusted until an output clock signal has a desired phase relationship with the input clock signal. Once the desired phase relationship is attained, the training procedure may be terminated and the DLL input may be switched to receive the data strobe signal.

Method and apparatus for training a DLL in a memory subsystem

In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address.

Two dimensional data randomization for a memory

In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Command queue for peripheral component

In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Test method using memory programmed with tests and protocol to communicate between device under test and tester

A system and method for testing a development device includes extracting multiple parameters of the development device from a product specification for the development device. The parameters being arranged in a predetermined first order. The parameters are stored in a testing data file. The testing data file can be input into a test bench system being coupled to the development device. The test bench system can test the development device.

System and method for automatic extraction of testing information from a functional specification

A software-implemented shared bus system model for modeling a shared bus system that includes a plurality of devices interconnected via a shared bus. The system model includes a first device model for partially modeling a first one of the plurality of devices, the first device model including a first modified logical module and a first modified I/O-specific module. The system model further includes a sharable module having provisioned therein first shareable data. The first shareable data is shareable by the first device model and another device model of the plurality of device models. The first shareable data represents I/O-specific data associated with the first device model that is also needed by the another device model of the plurality of device models during configuration of the shared bus system model. The first shareable data further represents data that would have been provisioned within the first device model if the first device model had been configured to closely mimic the data content of the first one of the plurality of devices, the first shareable data instead being provisioned in the shareable module.

Apparatuses and methods for modeling shared bus systems

A method for modeling and verifying a set of transactions between a set of master devices and a set of slave devices that are coupled via a bus. The method includes determining a set of dependencies for the set of transactions, executing the set of transactions on the bus, and observing the set of transactions for the dependencies. If the set of transactions does not comprise the dependencies, the method additionally includes logging a status for the set of transactions.

Methods and apparatus for modeling and verifying a set of PCI bus transactions

A system and method for generating a test case for testing a device to be connected to a computer is disclosed. A base test object is provided. The base test object defines test properties for a device. The base test object includes a transaction generator that generates transactions. An extending test object is created, the extending test object defines test properties for a distinct configuration of the device. The extending test object also inherits at least one test property of the base test object. The transaction generator is executed to generate several transactions for the test case, each of the transactions defining a stimulus being specifically designed to stimulate at least one test property of the distinct configuration of the device.

Method and apparatus for developing multiple test cases from a base test case

A system and method for comparing performance of two or more devices is disclosed. The method includes defining a workload. A workload object is provided. The workload object includes a transaction generator. A first test case is applied to a first device. Executing the transaction generator on a first test object produces the first test case. The first test object includes multiple first interface properties. Executing the transaction generator on the first test object produces a first set of transactions according to the first interface properties. The first set of transactions stimulates the defined workload in the first device. A second test case is applied to a second device. Executing the transaction generator on a second test object produces the second test case. The second test object includes multiple second interface properties. Executing the transaction generator on the second test object produces a second set of transactions according to the second interface properties. The second set of transactions stimulates the defined workload in the second device. A first test result from the first test case is compared to a corresponding second test result from the second test case.

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Cupertino, CA, United States of America

Douglas C Lee