International Business Machines Corporation

Douglas C Heaberlin

Leendert M Huisman

Leah M P Pastel

Thomas Webster Bartenstein

Patrick H Buffet

Glen E Richard

Raymond J Rosner

Yu H Sun

Leah M Pastel

L Owen Farnsworth

Francis Woytowich

Edward E Horton, Iii

Thomas F Mechler

A method, system and computer program product for diagnosing a bridging defect in an integrated circuit including multiple nodes are disclosed. Quiescent power supply current (I) of the integrated circuit (IC) is measured under multiple test vectors. Logic states of the nodes on the IC are also obtained under the multiple test vectors. The nodes are partitioned into sets based on their logic states under low-current test vectors. Large sets are further divided into subsets ('state-count subsets') based on the logic states of nodes under high-current test vectors. For large sets, explicit evaluation under the Ibridge fault model is performed only on pairs of nodes belonging to subsets having complementary state counts, to save system resources in computation. Exhaustive diagnosis considering all pairs of nodes on the IC is thus feasibly achieved due to the saving of system resources.

Exhaustive diagnosis of bridging defects in an integrated circuit including multiple nodes using test vectors and IDDQ measurements

A method for improving the signal-to-noise ratio in an Idefect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An Idefect is activated to generate Idefect current within the integrated circuit. An amount of Idefect current generated within each area is measured at the terminals provided thereto. Based on the Icurrent measurement on each area, an Icurrent map is created. By analyzing the Icurrent map, the presence and location of the defect is determined. Based on the determination, the Idefect is isolated.

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A method of testing a semiconductor device having a memory is disclosed. The method includes selecting a portion of the memory; testing the selected portion of the memory; designating the selected portion of the memory as a designated memory in response to an acceptable testing result; and storing data in the designated portion of the memory for retrieval at a later time. Provision for soft repair of the selected memory is made. Test data can be compressed before being stored in the designated memory.

Internal cache for on chip test data storage

A method for diagnosing defects in an integrated circuit comprising: providing a set of failing test patterns; for each failing test pattern in the set of test patterns determining if a single stuck-at fault could cause the failing test pattern and determining a node on which a defect causing the single stuck-at fault could reside; selecting those failing test patterns that could be caused by a single stuck-at fault; and for those selected failing test patterns determining a first set of sets of nodes, such that each of the selected failing test patterns could be caused by a stuck-at zero or a stuck-at one on at least one node from each set of nodes from the first set of sets of nodes.

Diagnosis of combinational logic circuit failures

A method for improving the signal-to-noise ratio in an I defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An I defect is activated to generate I defect current within the integrated circuit. An amount of I defect current generated within each area is measured at the terminals provided thereto. Based on the I current measurement on each area, an I current map is created. By analyzing the I current map, the presence and location of the defect is determined. Based on the determination, the I defect is isolated.

Method for locating IDDQ defects using multiple controlled collapse chip connections current measurement on an automatic tester

An incremental fault dictionary in which the diagnostic simulation results of current tests are stored for future use. Diagnostic simulation results are incrementally added to the fault dictionary, and information in the incremental fault dictionary is used to avoid expensive redundant fault simulations. The size of the incremental fault dictionary is maintained within user definable bounds by identifying and deleting faults that need not be maintained in the incremental fault dictionary. The incremental fault dictionary beneficially provides more accurate and faster diagnostics than a typical prior art diagnostic fault simulation.

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Underhill, VT, United States of America

Douglas C Heaberlin