Intel Corporation

Douglas Boom

Scott P Dubal

Mark V Montecalvo

Dave L Matheny

David M Lerner

Patrick L Connor

Elizabeth M Kappler

Matthew M Gilbert

Jordan J Rodgers

Eliel Louzoun

Kent C Lusted

Chris Pavlas

Nishantkumar Shah

Ronald Frederick Barbee

Vilkas Visotski

Nicholas Konkol

Arjun Anantharam

Technologies for monitoring networked computing devices using deadman triggers includes a network interface controller (NIC) configured to collect a pin state of at least one deadman trigger pin associated with a deadman trigger and determine whether a triggering event associated with the deadman trigger has been detected as a result of the comparison. The NIC is further configured to generate, in response to a determination that the triggering event has been detected, a status packet that is usable to identify the detected triggering event associated with the deadman trigger. Additionally, the NIC is configured to issue a stop transmission command to each of a plurality of egress packet transmission queues of the NIC and insert the generated status packet into at least one of the plurality of egress packet transmission queues for transmission to a target computing device. Other embodiments are described herein.

Technologies for monitoring networked computing devices using deadman triggers

Methods for implementing mini-mezzanine Open Compute Project (OCP) plug-and-play Network PHY Cards and associated apparatus. In accordance with one aspect, the MAC (Media Access Channel) and PHY (Physical) layer functions in one or more communication protocol stacks are split between a MAC block in a Platform Controller Hub (PCH) or processor SoC and a PHY card installed in a mezzanine slot of a platform and including one or more ports. During platform initialization operations, configuration parameters are read from the PHY card including a PHY card ID, and a corresponding configuration script is selected and executed to configure the PHY card for use in the platform. The configuration parameters are also used to enumerate PCIe devices associated with physical functions and ports supported by the PHY card.

Method to enable intel mini-mezz open compute project (OCP) plug-and-play network phy cards

Apparatuses, systems and methods associated with causing a physical layer (PHY) device are disclosed herein. In embodiments, an apparatus may include a memory device to store one or more activity lists associated with one or more external PHY devices, external to the apparatus, including the first external PHY device. The apparatus may further include a processor, that executes an engine, to receive a request for performance of the operation by the first external PHY device, identify an activity list associated with the first external PHY device from the one or more activity lists, identify an activity to effectuate performance of the operation from the activity list associated with the first external PHY device and cause the first external PHY device to perform the operation in accordance with the activity.

Physical layer device operation system and method

An apparatus and method for using conductive adhesive fibers as a data interface are disclosed. A particular embodiment includes: a first array of conductive adhesive fiber fastener pads configured for attachment to a first item; a second array of conductive adhesive fiber fastener pads configured for attachment to a second item, each pad of the first and second array being fabricated with a hook or loop removable fastener, each removable fastener being electrically conductive, the first array of pads being arranged to align with the second array of pads to create a plurality of independent electrical connections when the first item is removably attached to the second item, the plurality of independent electrical connections establishing a data interface connection between the first item and the second item.

Apparatus and method for using conductive adhesive fibers as a data interface

In an embodiment, the present invention includes a multicore processor with a front end unit including a fetch unit to fetch instructions and a decode unit to decode the fetched instructions into decoded instructions, a first core coupled to the front end unit to independently execute at least some of the decoded instructions, and a second core coupled to the front end unit to independently execute at least some of the decoded instructions. The second core may have a second power consumption level greater than a power consumption level of the first core and also heterogeneous from the first core. The processor may further include an arbitration logic coupled to the first and second cores to enable the second core to begin execution responsive to a start processor instruction present in the front end unit. Other embodiments are described and claimed.

Controlling an asymmetrical processor

The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network device driver is loaded during a machine boot, where the bus-to-network device driver is capable of sending machine bus commands over a network, providing access to the network for a network device driver, and distinguishing between received responses to the machine bus commands and other network traffic corresponding to the network device driver. Loading of the bus-to-network device driver can occur in response to an operating system load of bus drivers. For example, the bus-to-network device driver can be an iSCSI driver, and the operating system load of bus drivers can be the operating system load of SCSI drivers.

Network storage target boot and network connectivity through a common network device

In an embodiment, the present invention includes a multicoreprocessor with a front end unit including a fetch unit to fetch instructions and a decode unit to decode the fetched instructions into decoded instructions, a first core coupled to the front end unit to independently execute at least some of the decoded instructions, and a second core coupled to the front end unit to independently execute at least some of the decoded instructions. The second core may have a second power consumption level greater than a power consumption level of the first core and also heterogeneous from the first core. The processor may further include an arbitration logic coupled to the first and second cores to enable the second core to begin execution responsive to a start processor instruction present in the front end unit. Other embodiments are described and claimed.

Disclosed are exemplary embodiments for updating a networked machine having at least a dormant state and an active state. In various embodiments, when the machine it is a dormant state, it listens to a network for candidate updates, that is, updates that may be applicable to the machine. In some embodiments, determining the candidate update is an applicable update for the machine may be based at least in part on a variety of reasons, including testing if it has already been applied, does not actually update some aspect of the machine, conflicts with an existing configuration of the machine, conflicts with a policy of the machine, etc. The machine may cache some or all of the candidate updates or applicable updates, where a variety of rationales or policies may be used to control update retention. When the machine enters an active state, such as a power on or non-sleep mode, or other active state, the machine may validate integrity of an applicable update if not done while the machine was dormant, and optionally choose to install it.

Updating machines while disconnected from an update source

A directed audio system, a network interface communicatively coupled with a network, and a controller to receive, via the network interface, an estimate for a location from a locating device communicatively coupled with the network, and to cause the directed audio system to direct an audio signal based at least in part on an estimate for the location received from the locating device.

Growing community of inventors

Portland, OR, United States of America

Douglas Boom