United Memories, Inc.

Sony Corporation

Ramtron Corporation

Other

Promos Technologies, Inc

Nippon Steel Semiconductor Corporation

Inmos Limited

Nmb Semiconductor Company, Ltd.

Mosel Vitelic Corporation

Ramtron International Corporation

Nmb Semiconductor Corporation

Douglas Blaine Butler

Michael C Parris

Kim Carver Hardee

Oscar Frederick Jones, Jr

Ronald R Bourassa

Richard Allen Bailey

E Henry Stevens

Michael V Cordoba

S Sheffield Eaton, Jr

Thomas C Taylor

A twin cell architecture for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM utilizing an open bitline configuration is disclosed. The twin cell architecture disclosed has significant advantages over conventional designs in terms of power, radiation hardness and speed and does not require intermediate supply voltage bitline precharge while allowing for 6F2 memory cell layouts.

Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM

A switched capacitor charge sharing technique for integrated circuit devices which allows for efficient charge sharing and signal level generation of exact desired values, and wherein the signal levels of the circuits sharing the charge do not have to have the same voltage levels. In a particular embodiment of the technique of the present invention disclosed herein, a switched capacitor is used to share charge between, for example, two different signals or two different groups of signals. The size of the capacitor can be adjusted to obtain the required signal level of the various signals.

Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values

A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when in an active operational mode. A maximum level of through current is supplied when VIN=VREF with lower levels of through current at all other VIN voltages. In an integrated circuit device incorporating an input buffer as disclosed, two (or more) input buffers may be utilized per device input pin.

High-speed, low-power input buffer for integrated circuit devices

A DRAM refresh period adjustment technique based on the retention time of one or more unused memory cell(s) having characteristics very similar to the characteristics of the memory cell(s) with the shortest retention time used in the DRAM array. In a particular implementation of the technique of the present invention, the refresh period of a DRAM array is adjusted through the use of one or more of the DRAM bits that fail to meet the retention time requirement and have, therefore, been replaced by redundant DRAM bits. These replaced bits are then used to indicate the refresh period for the DRAM is the maximum it can be for the DRAM under then current operating conditions.

Refresh period adjustment technique for dynamic random access memories (DRAM) and integrated circuit devices incorporating embedded DRAM

A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time.

Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks

A dual access DRAM includes first and second sets of data lines. By adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors, data can be transferred to a second subarray by way of an additional set of data lines. The second set of data lines are additional internal read/write lines used in addition to the normal set of data lines. The second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small.

Dual access DRAM

A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (t) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (V) on the power-gating transistors.

Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM

An integrated circuit memory includes circuitry for individually activating word lines in a first one memory cell per bit operational mode, simultaneously activating at least two word lines in a second operational mode where two or more memory cells are dedicated to each data bit, and providing a word line sequence when first converting stored data in the array of memory cells from the first operational mode to the second operational mode. The word line sequence includes activating a first word line, developing a valid signal on a corresponding bit line, and then activating a second word line while the first word line is still active.

Dual word line mode for DRAMs

A refresh circuit is used for refreshing or masking from refresh non-contiguous subarrays in an integrated circuit memory array. At the initiation of each masked refresh cycle the address inputs, which normally are ignored, are evaluated to indicate which subarrays should be refreshed and which should be not refreshed. Power is saved due to the flexibility in determining which subarrays are refreshed at each new refresh cycle.

Non-contiguous masked refresh for an integrated circuit memory

A bandgap reference circuit includes a current-voltage mirror circuit having first, second, third, and fourth nodes, a transistor having a current path coupled between a source of supply voltage and the first node, a current mirror portion having an input coupled to the first node and a control terminal coupled to the fourth node, a serially coupled first resistor and first diode coupled between the output of the current mirror portion and ground, a serially coupled second resistor and second diode coupled between the third node and ground, a third diode coupled between the second node and ground, and a differential amplifier having a first input coupled to the fourth node, a second input coupled to the output of the current mirror portion for generating a bandgap reference voltage, and an output coupled to the gate of the transistor.

Bandgap reference circuit

A driver timing and circuit technique for a low noise charge pump circuit of particular applicability with respect to integrated circuit devices requiring voltage levels either more positive than or more negative than, externally supplied voltages. In accordance with the technique of the present invention, the pump capacitor is driven &ldquo;high&rdquo; by one transistor and &ldquo;low&rdquo; by another. By correctly sizing the devices driving them, each transistor can be turned &ldquo;off&rdquo; quickly and &ldquo;on&rdquo; slowly and, in an alternative embodiment, both transistors may be &ldquo;off&rdquo; at the same time resulting in &ldquo;tri-state&rdquo; operation. Timing is set such that both transistors are &ldquo;off&rdquo; when a third transistor connecting the intermediate node to the power supply is turned &ldquo;on&rdquo; and when a fourth transistor connecting the intermediate node to the pumped supply is turned &ldquo;on&rdquo; thereby preventing large dI/dt and resultant noise on the power supply sources.

Driver timing and circuit technique for a low noise charge pump circuit

A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Multi-chip memory apparatus and associated method

A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently &ldquo;self-aligned&rdquo; to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Technique for forming a borderless overlapping gate and diffusion contact structure in integrated circuit device processing

A delayed start oscillator includes an oscillator enable signal having first and second states thereof for selectively enabling and disabling the oscillator respectively. An oscillator output signal has first and second levels thereof responsive to the first state of the oscillator enable signal for providing an oscillator output signal. A timing circuit is coupled to a supply voltage line for providing a timing signal output indicative of a selected delayed start duration and a plurality of series connected inverting stages are coupled to receive the oscillator output signal and the timing signal. The oscillator output signal remains at a first level for the delayed start duration in response to the timing signal and subsequently transitions between the first and second levels at an operational frequency determined by the plurality of inverting stages until the oscillator enable signal transitions to the second state thereof. The delayed start oscillator is operational to provide an output clock signal at a constant rate following a selectively delayed startup time and can be used, for example, in dynamic memory cell-based integrated circuit devices incorporating a-self-refresh mode or other special modes of operation wherein an initial start-up delay in entering the particular mode is desired and in which the initial delay is longer than the clock period of the signal then controlling the mode.

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Colorado Springs, CO, United States of America

Douglas Blaine Butler