Advanced Micro Devices Corporation

Hewlett-packard Company

Other

Ati Technologies Ulc

Douglas Benson Hunt

Paul J Moyer

Russell C Brockmann

Gregory L Ranson

Gregg Bernard Lesartre

Steven T Mangelsdorf

Kai Troester

Philip Ng

Dale Calvin Morris

William Louie Walker

Jay E Fleischman

Richard Martin Born

Eric Christopher Morton

Patrick Knebel

William Evan Jones, Iii

Paul C Miranda

Jonathan P Lotz

John William Bockhaus

Elizabeth Morrow Cooper

Paul L Perez

Robert E Naas

Prasanta K Bhowmik

Tanuj Kumar Agarwal

Anasua Bhowmik

Richard H Lee

Systems, apparatuses, and methods for arbitrating threads in a computing system are disclosed. A computing system includes a processor with multiple cores, each capable of simultaneously processing instructions of multiple threads. When a thread throttling unit receives an indication that a shared cache has resource contention, the throttling unit sets a threshold number of cache misses for the cache. If the number of cache misses exceeds this threshold, then the throttling unit notifies a particular upstream computation unit to throttle the processing of instructions for the thread. After a time period elapses, if the cache continues to exceed the threshold, then the throttling unit notifies the upstream computation unit to more restrictively throttle the thread by performing one or more of reducing the selection rate and increasing the time period. Otherwise, the unit notifies the upstream computation unit to less restrictively throttle the thread.

Throttling while managing upstream resources

Systems, apparatuses, and methods for generating a measurement of write memory bandwidth are disclosed. A control unit monitors writes to a cache hierarchy. If a write to a cache line is a first time that the cache line is being modified since entering the cache hierarchy, then the control unit increments a write memory bandwidth counter. Otherwise, if the write is to a cache line that has already been modified since entering the cache hierarchy, then the write memory bandwidth counter is not incremented. The first write to a cache line is a proxy for write memory bandwidth since this will eventually cause a write to memory. The control unit uses the value of the write memory bandwidth counter to generate a measurement of the write memory bandwidth. Also, the control unit can maintain multiple counters for different thread classes to calculate the write memory bandwidth per thread class.

Quality of service dirty line tracking

Systems and methods are disclosed for domain specific predictive model for entity assessment and valuation. In one implementation, evaluation criteria are identified. Historical data is collected with respect to one or more entities. Based on the one or more evaluation criteria and the historical data, one or more scores are reverse engineered with respect to the one or more entities. Linear regression analysis is performed on the one or more scores to build a predictive model. Analyze a new entity using the same scoring system with pre-prescribed parameters. Using the predictive model, a valuation of an entity is computed. One or more aspects of the computed valuation are presented within an interactive interface using a sensitivity analysis approach.

Domain specific predictive model for entity assessment and valuation

A processing system suspends execution of a program thread based on an access latency required for a program thread to access memory. The processing system employs different memory modules having different memory technologies, located at different points in the processing system, and the like, or a combination thereof. The different memory modules therefore have different access latencies for memory transactions (e.g., memory reads and writes). When a program thread issues a memory transaction that results in an access to a memory module having a relatively long access latency (referred to as 'slow' memory), the processor suspends execution of the program thread and releases processor resources used by the program thread. When the processor receives a response to the memory transaction from the memory module, the processor resumes execution of the suspended program thread.

Thread switch for accesses to slow memory

Security key identifier remapping includes associating a system-level security key identifier to a local-level identifier requiring fewer bits of storage space. The remapped security key identifiers are used to receive, at a first compute complex of a processing system, a memory access request including a memory address value and a system-level security key identifier. The compute complex responds to the memory access request based on a determination of whether a security key identifier map of the first compute complex includes a mapping of the system-level security key identifier to a local-level security key identifier. In response to determining that the security key identifier map of the first compute complex does not include a mapping of the system-level security key identifier to the local-level security key identifier, a cache miss message may be returned without probing caches of the first compute complex.

Security key identifier remapping

A system includes a multi-core processor that includes a scheduler. The multi-core processor communicates with a system memory and an operating system. The multi-core processor executes a first process and a second process. The system uses the scheduler to control a use of a memory bandwidth by the second process until a current use in a control cycle by the first process meets a first setpoint of use for the first process when the first setpoint is at or below a latency sensitive (LS) floor or a current use in the control cycle by the first process exceeds the LS floor when the first setpoint exceeds the LS floor.

Scheduling memory bandwidth based on quality of service floorbackground

A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the request rate and the hit rate.

Prefetcher based speculative dynamic random-access memory read request technique

A method of monitoring, by one or more cores of a multi-core processor, speculative instructions, where the speculative instructions store data to a shared memory location, and where a semaphore, associated with the memory location, specifies the availability of the memory location to store data. One or more speculative instructions are flushed based on when the semaphore specifies the memory location is unavailable. Any further speculative instructions are suppressed from being issued based on a count of flushed speculation instructions above a specified threshold, executing the speculative instructions when the semaphore specifies the memory location is available, and storing the data to the memory location.

Suppression of speculative accesses to shared memory locations at a processor

A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

I/O writes with cache steering

A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID.

Instruction fetch translation lookaside buffer management to support host and guest O/S translations

A cache is provided, including a data array having a plurality of entries configured to store a plurality of different types of data, and a tag array having a plurality of entries and configured to store a tag of the data stored at a corresponding entry in the data array and further configured to store an identification of the type of data stored in the corresponding entry in the data array.

Cache for storing multiple forms of information and a method for controlling a cache storing multiple forms of information

A processor is provided. The processor including a cache, the cache having a plurality of entries, each of the plurality of entries having a tag array and a data array, and a remapper configured to create at least one identifier, each identifier being unique to a process of the processor, and to assign a respective identifier to the tag array for the entries related to a respective process, the remapper further configured to determine a replacement value for the entries related to each identifier.

Cache and a method for replacing entries in the cache

Interference in a branch history table of a microprocessor is reduced by methods and apparatus which predict the outcome of branch instructions (taken or not taken) through a combination of static and dynamic prediction techniques. Static prediction information (e.g., a compiler hint) may be stored in instruction memory, and dynamic prediction information is stored in a branch history table. A branch prediction results from an exclusive OR of static and dynamic prediction information. After execution of a branch instruction, an indication as to whether a branch was taken or not taken is exclusively ORed with the static prediction information for the branch instruction, and the result of this exclusive OR is used to update an appropriate entry in the branch history table. Using the methods and apparatus disclosed herein, two well-behaved branches may share an entry in a branch history table, yet not interfere with one another (even when the two well-behaved branches include one which is mostly taken, and one which is mostly not taken).

Growing community of inventors

Fort Collins, CO, United States of America

Douglas Benson Hunt