Sun Microsystems, Inc.

Xerox Corporation

Douglas B Lee

Pradeep S Sindhu

Bjorn O Liencres

Jean-Marc Frailong

Jung-Herng Chang

Jorge Cruz-Rios

Tung Pham

A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue. By buffering the old cache line in the pending write-back controller, the cache control system allows the new cache line to be requested before the old cache line is written back to main memory thereby reducing the cache line replacement latency period.

Methods and apparatus for creating a pending write-back controller for a

A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher clients, each of which is coupled to a separate system bus. The bus allows the cache controller to provide independent processor-side access to the cache and allows the bus watchers to handle functions related to bus-snooping. An arbiter is employed to allow the bus to be multiplexed between the bus watchers and cache controller. Flow control mechanisms are also employed to ensure that queues receiving packets or arbitration requests over the bus never overflow. A default grantee mechanism is employed to minimize the arbitration latency due to a request for the bus when the bus is idle.

Apparatus and method for a synchronous, high speed, packet-switched bus

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San Francisco, CA, United States of America

Douglas B Lee