Lsi Logic Corporation

Monterey Design Systems, Inc.

Synopsys, Inc.

Photonic International Pte. Ltd.

Douglas B Boyle

James S Koford

Michael D Rostoker

Ranko L Scepanovic

Edwin R Jones

Lawrence Thomas Pileggi

Sharad Malik

Abhijeet Chakraborty

Gary K Yeap

Majid Sarrafzadeh

Feroze P Taraporevala

Salil Ravindra Raje

Lilly Shieh

Dennis Yamamoto

David Gluss

Tong Gao

Eric McCaughrin

Emre Tuncer

Alexander E Andreev

Stanislav V Aleshin

Alexander S Podkolzin

Valeriy B Kudryavtsev

Christopher J Dunn

Birendra Dutt

Patrik D'Haeseleer

Robert E Shortt

Satyamurthy Pullela

Joseph T Rahmeh

Dinesh D Gaitonde

Edwin E Jones

Altan Odabasioglu

Sam Jung Kim

Archie Li

Yau-Tsun Steven Li

Satamurthy Pullela

Georgia Lazana

A photonics-optimized multi-processor system may include a plurality of processor chips, each of the processor chips comprising at least one input/output (I/O) component. The multi-processor system may also include first and second photonic components. The at least one I/O component of at least one of the processor chips may be configured to directly drive the first photonic component and receive a signal from the second photonic component. A total latency from any one of the processor chips to data at any global memory location may not be dominated by a round trip speed-of-light propagation delay. A number of the processor chips may be at least 10,000, and the processor chips may be packaged into a total volume of no more than 8 m. A density of the processor chips may be greater than 1,000 chips per cubic meter.

Photonics-optimized processor system

The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists&#x2014;netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics&#x2014;delay, area, congestion, power, etc. 'Dual' refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

Placement method for integrated circuit design using topo-clustering

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.

Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms

A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design

The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.

A design tool for integrated circuits includes a placement tool which places logic gates and interconnect components concurrently. Probabilistic interconnect models are used to represent the collection of possible interconnect routings that provide acceptable circuit performance and routing area.

System and method for concurrent placement of gates and associated wiring

A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

System and method for concurrent buffer insertion and placement of logic gates

This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.

Method for logic optimization for improving timing and congestion during placement in integrated circuit design

A large number of possible cell placements for an integrated circuit chip are evaluated to determine which has the highest fitness in accordance with a predetermined criteria such as interconnect congestion. Each cell placement, which constitutes an individual permutation of cells from a population of possible permutations, is represented as an initial cell placement in combination with a list of individual cell transpositions or swaps by which the cell placement can be derived from the initial cell placement. A cell placement can be genetically mutated and/or inverted by adding swaps to the list for its cell placement which designates cells to be transposed. Genetic crossover can be performed by transposing swaps between the lists for two cell placements. This cell representation and transposition method enables any type of cell transposition to be performed without loss or duplication of cells or generation of illegal placements.

Cell placement representation and transposition for integrated circuit

A subscriber station for decrypting and decompressing data is provided on a single chip. The chip includes a DES decryption unit for performing decryption of incoming data with a DES key, a public key decryption unit for decrypting the DES key, a general purpose microprocessor for performing decompression, and a Secure Buffer for protecting the decrypted data prior to decompression. The chip includes an embedded key for the public key decryption unit and a bus for providing a data communication path between the microprocessor and the decryption units.

Microprocessor having instruction set extensions for decryption and

A method for optimizing layout design using logical and physical information performs placement, logic optimization and routing and routing estimates concurrently. In one embodiment, circuit elements of the integrated circuit is partitioned into clusters. The clusters are then placed and routed by iterating over an inner-loop and an outer-loop according to cost functions in the placement model which takes into consideration interconnect wiring delays. Iterating over the inner-loop, logic optimization steps improves the cost functions of the layout design. Iterating over the outer-loop, the size of the clusters, hence the granularity of the placement, is refined until the level of individual cells is reached. The present method is especially suited for parallel processing by multiple central processing units accessing a shared memory containing the design data base.

Method for providing performance-driven logic optimization in an

A system for providing information to memory within a local device is provided herein. The system initially receives information transmitted from a remote location and reads predetermined data, including start and end addresses, within the local device. The system computes a checksum based on information received from the remote location and the predetermined data and compares a predetermined checksum to the received information checksum. If the predetermined checksum does not equal the received information checksum, the system requests retransmission of information and repeats the preceding steps (receiving information, computing a checksum, and comparing) until the predetermined checksum equals the received information checksum. The system then provides the valid information to local device memory. The invention may execute a protocol to receive information packets and store the information packets in appropriate memory locations after receiving the information. The system may copy information from the remote location directly into local device memory. The system is implemented on a single chip and provides information to memory of a local device. The system utilizes minimal non-volatile memory and comprises a microprocessor and registers including a start register, an end register, and a checksum register, and a communications interface. The communications interface receives information from a remote device, the microprocessor receives information from the communications interface and evaluates whether information received is valid, and the microprocessor passes valid information to RAM for execution.

Single chip systems using general purpose processors

The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.

Growing community of inventors

Palo Alto, CA, United States of America

Douglas B Boyle