Qorvo Us, Inc.

Raytheon Company

Rf Micro Devices, Inc.

Douglas Andrew Teeter

Ming Ji

Bhavin Shah

Praveen Varma Nadimpalli

Edward T Spears

Mohsen Haji-Rahim

Raghuveer Mallavarpu

Aryeh Platzker

Hien D Bui

William Kent Braxton

Nick Marcoux

Disclosed is an amplifier having a carrier amplifier configured as a common-emitter carrier power stage and a peaking amplifier configured as a common-emitter peaking power stage. Further included is power adaptive biasing circuitry coupled between the carrier amplifier and the peaking amplifier, wherein the power adaptive biasing circuitry is configured to sense direct current base voltages of the common-emitter carrier power stage and to generate control currents that debias the common-emitter carrier power stage in response to the current base voltages of the common-emitter carrier power stage.

Doherty power amplifier

The present disclosure relates to a radio frequency (RF) communications system including an RF power amplifier (PA), a bias circuit, and a protection circuit. The RF PA has an amplifier control terminal and a power supply terminal, the bias circuit is coupled to the amplifier control terminal, and the protection circuit is coupled between the bias circuit and the power supply terminal. Herein, the protection circuit is configured to reduce a current through the power supply terminal using the bias circuit via the amplifier control terminal when the RF PA is in an operation mode and a magnitude of a voltage at the power supply terminal exceeds a protection threshold. Further, the protection circuit is configured to be open and does not allow a current to pass through when the RF PA is in a standby mode.

Low leakage protection circuit for RF power amplifier

Disclosed is an integrated circuit module that includes a first die having a plurality of hot regions and at least one cool region when operating under normal conditions. The first die with a top surface includes at least one power amplifier that resides in the plurality of hot regions. The integrated circuit module also includes a second die. The second die has a bottom surface, which is adhered to the top surface of the first die, wherein any portion of the bottom surface of the second die that is adhered to the top surface of the first die resides exclusively on the at least one cool region. In at least one embodiment, the first die is an RF power amplifier die and the second die is a controller die having control circuitry configured to control the at least one power amplifier that is an RF power amplifier type.

Integrated circuit module having a first die with a power amplifier stacked with a second die and method of making the same

An RF electronics module includes a grounding plate, a non-conductive substrate, a number of conductive vias, RF PA circuitry, and RF power detection circuitry. The non-conductive substrate is over the grounding plate. The conductive vias extend parallel to one another from a surface of the non-conductive substrate opposite the grounding plate through the non-conductive substrate to the grounding plate. The RF PA circuitry is coupled to the grounding plate through a first one of the conductive vias. The RF power detection circuitry is coupled to a second one of the conductive vias and configured to measure a signal induced in the second one of the conductive vias due to electromagnetic coupling with the first one of conductive vias. The first one of the conductive vias is adjacent to the second one of the conductive vias.

Compact power detection circuit utilizing ground via coupling

A power amplification circuit having three modes of operation and a single switch is disclosed. Only one switch is used to control three different load impedance levels, one load impedance level for each mode of operation. The remaining 'switching' results from selectively biasing each power amplification path by turning ON or OFF amplifiers. A series L-C and a switch are used to control the load impedance. Additional modes of operation may also be created without requiring any additional switch. Further, multiple modes of operation may be implemented using no switches.

Modified dynamic load scaling (MDLS) technique for implementing high efficiency low power mode operation

The present invention is a parallel RF amplifier circuit that selects between a high power side (HPS) and a low power side (LPS), depending upon output power. A chain matching network couples an LPS output to an HPS output for improved efficiency at lower output power. When the HPS is selected, the LPS output is disabled, and when the LPS is selected, the HPS output is disabled When the HPS is selected, large signal voltage swings from the collector of the HPS amplifier may be multiplied through the chain matching network, and may cause negative voltage swings at the LPS collector, which may degrade linearity and efficiency of the HPS amplifier by driving currents into the disabled LPS amplifier. Therefore, the present invention includes LPS bias circuitry to minimize impacts of negative voltage swings at the LPS output.

Radio frequency parallel amplifier

A method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance C,and a drain-gate capacitance C,, both being functions of a gate-source voltage V,and a drain-source voltage V,. The s-parameters of the transistor are measured and curve fitting is applied to the measured s-parameters to establish small signal model parameters. The small signal model parameters include gate-source capacitance C,as a function of V,and V,and gate-drain capacitance C,as a function of V,and V,. Curve fitting is applied to C,and C,to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to express a gate-source charge Q,and a gate-drain charge Q,as functions of V,and a gate-drain voltage V,in a large signal model for the transistor.

Large signal model for a pseudomorphic heterojunction electron mobility transistor

A transistor device having a plurality of transistor cells. Each one of the cells has a control electrode for controlling a flow of carriers through a semiconductor. The device has an input node. A plurality of filters is provided. Each one of the filters is coupled between the input node and a corresponding one of the control electrodes of the plurality of transistor cells. In one embodiment of the invention, pairs of the control electrodes are connected to a common region and wherein each one of the filters is coupled between the input node and a corresponding one of the common regions. The semiconductor provides a common active region for the plurality of transistor cells. Each one of the filters comprises: a conductive layer; a dielectric layer disposed on the conductive layer; a resistive layer disposed over the dielectric layer; a conductive electrode disposed in electrical contact with a first portion of the resistive layer and providing the input node; and, a connector in electrical contact with a second portion of the resistive layer such second portion of the resistive layer being displaced from the first portion of the resistive layer, such connector passing through the dielectric and being in electrical contact with the first conductor.

Growing community of inventors

Lexington, MA, United States of America

Douglas Andrew Teeter