Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Nxp B.v.

Douglas Alan Garrity

Brandt Braswell

Patrick Lee Rakers

Ryan Haoyun Wu

Maik Brett

Xiankun Jin

Mohammad Nizam U Kabir

Youssef H Atris

Mohammad Nizam Kabir

Thierry Cassagnes

Mariam Hoseini

David R LoCascio

Ira G Miller

Ahmad H Atriss

Michael McGowan

Danny A Bersch

Patrick Drennan

David Locascio

James F McClellan

Kumar Abhishek

Troy L Stockstad

David J Anderson

Robert S Jones, Iii

Mike Robert Garrard

Juxiang Ren

Tao Chen

Bruce Michael Newman

Rakesh Shiwale

Zhou Zhixu

Steven P Allen

Mark Lehmann

Brad D Gunter

Mark Stachew

Chunhe Zhao

Christopher J Cavanagh

Mohammad Nlzam U Kablr

Paul Rene DeRouen

Andrea Eberhardt

A radar system, apparatus, architecture, and method are provided with a transmitter that produces a plurality of distinct FanTOM signals that are transmitted as N RF-encoded transmit signals in an overlapped fashion such that the pulse repetition interval and frame length are kept short; a receiver that processes target return signals reflected from the N RF-encoded transmit signals with a mixer to produce an IF signal which is filtered with one or more notch filters clocked with a sampling clock frequency to control harmonic notch frequencies to suppress transmitter spill-over and close-in self-clutter interference, thereby producing a filtered IF signal that is converted to a digital signal with an analog-to-digital converter that is clocked with the sampling clock frequency; and a radar processor that processes the digital signal to generate a range spectrum comprising N segments that correspond, respectively, to the N RF-encoded transmit signals.

Frequency and time offset modulation (FANTOM) chirp MIMO automotive radar with N-path notch filter

A radar system utilizing a linear chirp that can achieve a larger MIMO virtual array than traditional systems is provided. Transmit channels transmit distinct chirp signals in an overlapped fashion such that the pulse repetition interval is kept short and the frame is kept short. This alleviates range migration and aids in achieving a high frame update rate. The chirp signals from differing transmitters can be separated on receive in the range spectrum domain, such that a MIMO virtual array construction is possible. Distinct chirps are delayed versions of the first chirp signal. Chirps overlap in the fast-time domain, but due to delay, there is separation in the range spectrum domain. When the delay is at least the instrument round-trip delay, transmitters are separable. Further, the wavelengths are identical across transmitters such that there is no residual-range versus angle ambiguity issue present in the claimed frequency-offset modulation range division MIMO system.

Frequency and time offset modulation chirp MIMO radar

A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal that is applied to a waveform generator having a frequency offset generator and a plurality of single channel modulation mixers configured to generate a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Method and system for frequency offset modulation range division MIMO automotive radar using I-channel only modulation mixer

A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal to produce a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Method and system for frequency offset modulation range division MIMO automotive radar

Body text indent&#x2014;does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.

Analog-to-digital converter (ADC) testing

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage with reduced capacitor mismatch sensitivity

An on-chip built-in self-test (BIST) circuit () uses a controller (), analog-to-digital converter (ADC) (), and digital-to-analog converter (DAC) () to sense voltage and/or temperature measures at predetermined circuit locations (), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus () to the analog block, and to process analog test signals received over a second bus () from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.

Non-intrusive on-chip analog test/trim/calibrate subsystem

A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.

SNDR improvement through optimal DAC element selection

A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a common-mode reference voltage generation circuit uses one or more additional sampling switched capacitors to selectively couple the first and second reference voltages to the amplifier input during the gain phase when the input voltage is between the high and low threshold voltages using a switching configuration of switches that are controllable to connect the sampling switched capacitors to the one or more central nodes in the sampling phase, and to connect the amplifier output in feedback to the input sampling circuit in the gain phase while simultaneously connecting the one or more central nodes to the first amplifier input.

Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage

A sigma-delta (&#x3a3;&#x394;) analog-to-digital converter (ADC) comprises a main &#x3a3;&#x394; modulator configured to receive an analog input signal at a main &#x3a3;&#x394; modulator input and to provide a main digital output signal representative of the analog input signal and an auxiliary &#x3a3;&#x394; modulator configured to receive an auxiliary input signal at an auxiliary &#x3a3;&#x394; modulator input and to provide an auxiliary digital output signal, wherein the &#x3a3;&#x394; ADC comprises a shared integrator stage, the shared integrator stage is configured to be used by the main &#x3a3;&#x394; modulator and the auxiliary &#x3a3;&#x394; modulator, wherein, alternatingly, the shared integrator stage is selectively communicatively coupled to receive the analog input signal when configured to be used by the main &#x3a3;&#x394; modulator and selectively communicatively coupled to receive the auxiliary input signal when configured to be used by the auxiliary &#x3a3;&#x394; modulator.

Dual sigma-delta analog-to-digital converter

A method and circuit for testing an analog-to-digital converter (ADC) are provided. The method comprises: coupling a single-ended output of an analog signal source to a differential input of an amplifier; coupling a differential output of the amplifier to a differential input of the ADC; alternately providing first and second test signals from the single-ended output of the analog signal source to first and second input terminals of the differential input of the amplifier; amplifying the first and second test signals to generate amplified differential signals at the differential output of the amplifier; providing the amplified differential signals to the differential input of the ADC; and determining if an output of the ADC is as expected. An offset may also be provided to the differential output of the amplifier. The method allows an ADC having a differential input to be tested using a digital-to-analog converter (DAC) having a single-ended output.

Method for testing differential analog-to-digital converter and system therefor

A method and circuit for generating ramped voltages are provided. The ramp voltage generator circuit includes: a switched-capacitor amplifier having an input terminal, an output terminal, a sampling capacitor switchably coupled to the input terminal, and a gain capacitor switchably coupled to the output terminal; and a current source having a terminal coupled to a supply terminal, and a terminal coupled to the input terminal. The ramp voltage generator circuit may be coupled to test an analog-to-digital converter (ADC).

Ramp voltage generator and method for testing an analog-to-digital converter

A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

Digital to analog converter with current steering source for reduced glitch energy error

A non-overlapping clock generator circuit supplies clock signals to a stage of a pipelined ADC, which includes parallel switched capacitor circuitry. The non-overlapping clock generator circuit includes: a first trigger generation circuit that generates first and second trigger signals; a second trigger generation circuit that generates third and fourth trigger signals; a first clock generation branch that receives the first, second and fourth trigger signals and generates first sampling cycle and delayed sampling cycle clock signals; a second clock generation branch that receives the first, second and third trigger signals and generates second sampling cycle and delayed sampling cycle clock signals; a third clock generation branch that receives the second trigger signal and generates first gain cycle and delayed gain cycle clock signals; and a fourth clock generation branch that receives the first trigger signal and generates second gain cycle and delayed gain cycle clock signals.

Non-overlapping clock generator circuit and method

A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Growing community of inventors

Gilbert, AZ, United States of America

Douglas Alan Garrity