Hewlett-packard Company

Convex Computer Corporation

Douglas A Oppedahl

Bryan D Marietta

Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Apparatus, systems and methods for controlling electronic memories

Apparatus systems and methods for controlling electronic memories

Circuitry 300 is disclosed for isolating faults in a path 304 transmitting data words each having at least one data bit and at least one parity bit. Circuitry 300 includes a plurality of exclusive-OR gates 303 each having a first input coupled to the data path 304 for receiving a bit of a one of the data words being transmitted along path 304. A plurality of multiplexers 305 are also provided, each multiplexer 305 including a first input coupled to an output of a corresponding one of the exclusive-OR gates 303 and a control signal input for receiving a control signal. A plurality of registers 306 have an input coupled to an output of a corresponding one of the multiplexers 305 and an output coupled to a second input of a corresponding one of the exclusive-OR gates 303 and a second input of the corresponding one of the multiplexers 305. Each multiplexer 305 is operable to pass a bit presented at the output of the corresponding exclusive-OR gate 305 to the corresponding register 306 in response to a first state of the control signal and pass a bit presented at the output of the corresponding register 306 to the input of the corresponding register 306 in response to a second state of the control signal.

Apparatus, systems and methods for isolating faults during data

Scanning circuitry 300 is provided which includes first input circuitry 302 which is operable to transfer bits of received data in response to a first clock signal. Second input circuitry 303 is also provided which is operable to transfer the bits of received data in response to a second clock signal. At least one first storage device 307 is provided which is operable to transfer bits of data received from the first input circuitry 302 in response to the first clock signal. At least one second storage device 308 is provided which is operable to transfer bits of data received from the second input circuitry 303 in response to the second clock signal. First output circuitry 309 is provided which is operable to transfer bits of data received from the at least one first storage device 307 in response to the second clock signal. Further, second output circuitry 310 is provided which shifts bits of data received from the at least one second storage device 308 in response to the second clock signal. A multiplexer 311 selects between bits of data received from the first output circuitry 309 and bits of data received from second output circuitry 310 in response to respective first and second states of a control signal.

Growing community of inventors

Garland, TX, United States of America

Douglas A Oppedahl