Analog Devices,inc.

Douglas A Mercer

William G J Schofield

David H Robertson

Peter R Holloway

David C Reynolds

Christopher W Mangelsdorf

Ernest T Stroud

Michael P Timko

Peter Real

A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit. The load compensation circuit provides a first compensation load value upon the clock driver when data at the first and second data inputs is non-changing and provides a second compensation load value relative upon the clock driver when data at the first and second data inputs is changing such that a sum of the first load value and the first compensation load value equals a sum of the second load value and the second compensation load value.

Latch with data jitter free clock load

Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.

Current DAC code independent switching

A digital to analog converter circuit is segmented into a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit and a sub-digital to analog converting unit including a current source connected to a plurality of cascode units. A cascode bias unit is operatively connected to each cascode unit of the main digital to analog converting unit so as to bias each current source of the main digital to analog converting unit to operate at a same drain voltage. A second cascode bias unit is operatively connected to each cascode unit of the sub-digital to analog converting unit so as to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage. A reference voltage source is operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit. The tying of the reference voltage source to both cascode bias circuits causes the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.

Digital/analog converter including gain control for a sub-digital/analog converter

A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

Differential time sampling circuit

A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

Calibrated current source

A current switching cell for a multi-cell DAC, each cell having a data input and an analog output and including a current switching circuit having a current node; a current definition circuit for providing current to the current switching circuit at the current node; the current definition circuit having a parasitic coupling between the input and the current node; a driver circuit responsive to a data input for actuating the current switching circuit to provide an analog output from the current from the current definition circuit; and a control circuit responsive to at least one common control signal for controlling the current definition circuit and isolating the parasitic coupling between the current node and the common control signal; the driver circuit may also have a parasitic coupling between its driver input and the current node and the control circuit may isolate the parasitic coupling between the current node and the driver input.

Current switching cell for digital to analog converter

A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.

Digital to analog interface with equalized total signal delay and method of making it

A differential current switch including a differential switch pair of transistors having first and second complementary control inputs which receive first and second complementary signals so as to be controlled by a control signal with equal delay from a clock signal. A first set of switching transistors is coupled to provide the first complementary signal which controls the first complementary control input of the differential switch pair. A second set of switching transistors is coupled to provide the second complementary signal which controls the second complementary control input of the differential switch pair. First delay transistor pairs are coupled to the complementary outputs of the cross coupled inverter and have the characteristic that the fall times of its outputs are greater than the rise time of its outputs. Second delay transistor pairs are coupled to the first delay transistor pairs and have the characteristic that the rise times of its outputs are greater than the fall times of its outputs. The second delay transistor pairs are coupled to the first and second sets of switching transistors such that a first output of the second delay transistor pairs provides a first input signal to the first set of switching transistor pairs and a second input signal of the second set of switching transistor pairs, and a second output of the second delay transistor pairs provides the second input signal to the first set of switching transistor pairs and the first input signal of the second set of switching transistor pairs.

Differential current switch

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

Skewless differential switch and DAC employing the same

A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementarry signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant. Capacitors are included to maintain effectively constant the base voltages of the two switch transistors during the time that the two additional switches are open.

D/A converter with differential switching circuit providing symmetrical

A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementary signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant. Capacitors are included to maintain effectively constant the base voltages of the two switch transistors during the time that the two additional switches are open.

A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.

Current mode sample-and-hold amplifier

A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

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Bradford, MA, United States of America

Douglas A Mercer