Sun Microsystems, Inc.

Transmeta Corporation

Cswitch Corporation

Blue Armor Technologies, LLC

Douglas A Laird

Godfrey P D'Souza

James B Burr

Malcolm J Wing

Dana How

John William Hayes

Edmund Joseph Kelly

Jay B Patel

James F Testa

Robert K Yu

Robert F Cmelik

David Roger Ditzel

Colin Neal Murphy

Grzegorz B Zyner

Pohrong Rita Chu

Ivo J Dobbelaere

Charles Andrew Gram

Suresh Subramaniam

Mukunda Krishnappa

Jason Golbus

Kevin James

Sunil Kaul

Dave Trossen

Colin B Hunter

Methods and apparatus for a Secure Time Communication System () are disclosed. One embodiment of the invention provides secure and non-interactive communication of clock information over an unsecured communications channel. This communication provides perfect forward secrecy, while detecting and blocking message spoofing, message replay, denial of service and cryptographic performance attacks. This mechanism also bounds the effect of message delay manipulation. The mechanism consists of two components, a filtered time encryptor () and a filtered time decryptor (). The filtered time encryptor () produces a message in two parts; a time token followed by an encrypted message body. The time token is used as a filter to detect most attacks and to determine the message key.

Secure time communication system

A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

Heterogeneous configurable integrated circuit

A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.

Combining hardware and software to provide an improved microprocessor

An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This 'pocket tie' is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

Back-biasing in asymmetric MOS devices

A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.

Dynamic clocked inverter latch with reduced charge leakage

A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.

Static logic circuit with improved output signal levels

A package and packaging technique for enhancing performance of critical chips within an electronic device, wherein the critical chips comprise an integrated circuit. The package includes a main package incorporating a first integrated circuit coupled to a substrate board. At least one package having a second integrated circuit is mounted to the main package in order to reduce (i) propagation delay for data to transfer between critical chips within the main package and one of the plurality of packages or between the critical chips within the plurality of packages and (ii) total footprint area. The method for implementing such a package including the steps of packaging the first and second integrated circuits and electrically coupling these integrating circuits together in a mounted position.

Ball grid array packages for high speed applications

Growing community of inventors

Los Gatos, CA, United States of America

Douglas A Laird