Unisys Corporation

Douglas A Fuller

Joseph P Kerzman

David C Johnson

Kenneth L Engelbrecht

Michael J Rieschl

John Steven Kuslak

Peter B Criswell

Donald C Englin

James Edward Rezek

David P Williams

Carl R Crandall

Robert H Andrighetti

Robert J Palermo

Thomas D Hartnett

Ronald G Arnold

Kenichi Tsuchiya

Gerald G Fagerness

Michael C Otto

Richard F Paul

Louis B Bushard

Duane A Schroeder

Gregory Allen Marlan

Duane G Kurth

Matthew E Trautman

Linda J Brock

Edward C Fisher

Forest F Crocker

Lnda J Brock

A method includes retrieving, by a processor, a first entry from a global wait list as a current waiting lock. The method further includes decreasing, by the processor, a deadlock timer of the current waiting lock. The method further includes determining, by the processor, whether the deadlock timer equals zero. The method further includes appending, by the processor, the current waiting lock to an end of a deadlock victim selection list, if the deadlock timer equals zero. The method further includes selecting, by the processor, a victim from the deadlock victim selection list.

Systems and methods for implementing a multi-host record lock deadlock feedback mechanism

A method includes determining, by a processor, whether a program check condition exists. The method further includes determining, by the processor, whether a lock descriptor of a lock in a file lock table satisfies an unlocking condition. The method further includes releasing, by the processor, the lock by setting the lock descriptor's host identifier as zero. The method further includes determining, by the processor, whether any lock in the file lock table satisfies a lock conflict condition. The method further includes determining, by the processor, whether the file lock table includes any lock descriptor that satisfies a locking condition. The method further includes creating, by the processor, a new lock using the lock descriptor that satisfies the locking condition.

Systems and methods for implementing a multi-host record lock mechanism

A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the data processing system. Thus, errors in the control store memory can be handled seamlessly and efficiently, without requiring a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the error.

System and method for detecting and recovering from errors in a control store of an electronic data processing system

A system and method for performing dynamic partitioning operations within a data processing system is disclosed. According to one embodiment, the current invention provides a system that allows an unit to be added to an executing data processing partition. The partition may include a shared resource that is receiving requests from other units that are already included within the partition. The inventive system includes means for programmably enabling the unit to the shared resource. Once the unit is so enabled, the system synchronizes the request arbitration being performed by this unit with the arbitration activities occurring within other units requesting access to the shared resource. This synchronization process prevents two units from attempting to simultaneously access the shared resource.

System and method to support dynamic partitioning of units to a shared resource

A cache arrangement of a data processing system provides a cache flush operation initiated by a command from a maintenance processor. The cache arrangement includes a cache memory, a mode register, and a controller. The mode register is settable by the maintenance processor to one of first and second values. The controller selectively writes all of the modified information in the cache memory to the system memory responsive to the command. Also in response to this command, all of the information is invalidated in the cache memory if the mode register is set to the second value. In one embodiment, none of the information except the modified data is invalidated if the mode register is set to the first value. The second value may be utilized to efficiently reassign one or more cache memories to a new partition.

Cache with integrated capability to write out entire cache

A system and method for selectively injecting parity errors into instructions of a data processing system when the instructions are copied from a read buffer to a first level cache. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the read buffer. The error-injection system also includes programmable operating modes whereby error injection will occur during, for example, every copy back from the read buffer to the first level cache, or alternatively, during only a selected copy back sequence. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from a second level cache or storage device.

First level cache parity error inject

A data processor is disclosed that executes a number of microcode instruction words. Each of the microcode instruction words has a bit field reserved to indicate which, if any, event counters are to be incremented. This enables the number of executions of a particular microcode instruction word to be counted. By simply changing the microcode bits in the bit fields of the microcode instruction words, the event counter can be programmed to count any number or pattern of microcode instruction word executions. In one embodiment, there is a one-to-one correspondence between each bit in the bit field and each event counter. In another system, the bits in the bit field are decoded to provide an address that selects selected event counters.

Event counter

Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.

Method of using a four-state simulator for testing integrated circuit

Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.

Method and apparatus for performing microcode paging during instruction

A method and apparatus for efficiently identifying and resolving conflicts between conflicting cell substitution recommendations. Unlike the prior art, the present invention provides a resolving means within a data processing system to identify and resolve conflicting cell substitution recommendations. The resolving means may categorize the cell substitutions in accordance with a number of predetermined cell substitution types, wherein each of the cell substitution type may be assign a predetermined priority value. Thereafter, the resolving means may identify conflicting cell substitution recommendations, and resolve the conflicts in accordance with the predetermined priority scheme.

Method and apparatus for resolving conflicts between cell substitution

A method and apparatus for efficiently optimizing a circuit design by substituting identified cells within the circuit design with logically equivalent cells having different drive strengths. The present invention eliminates the need to update the design database and to place and route the circuit design during each design iteration. Rather, an improved extraction tool is provided which incorporates a cell substitution list, and updates the RC file therefrom. The updated RC file is used by the timing analysis tool to determine if the updated design will meet the design specification. After the design meets the design specification, a final place and route may be performed.

Method and apparatus for performing drive strength adjust optimization

A method and apparatus for efficiently performing timing analysis on a circuit design. The present invention essentially provides a hybrid between a path enumeration algorithm and a critical path algorithm. As such, the present invention increases the number and degree of timing violations reported by a Critical Path Analysis (CPA) algorithm, while maintaining a performance advantage over a Path Enumeration (PE) algorithm. This is accomplished by providing a number of 'pseudo' clocks to selected latches within the circuit design database, thereby tricking the CPA algorithm into reporting more timing violations than would otherwise be reported.

Method and apparatus for performing timing analysis on a circuit design

A self-timing clock generator for use with a precharged Static Random Access Memory (SRAM). The invention asynchronously switches the memory clock pulse to a precharge signal upon recognition of completion of a memory access cycle. Recognition of completion of the memory access cycle is performed in one of two ways. The first method monitors for the existence of a preprogrammed memory-completion bit which becomes active at the same time that read or write data becomes valid at the data outputs. The second method monitors for the existence of a memory-completion bit generated through the use of an odd parity generator. An alternate clocking method is provided to bypass the asynchronous self-timing clock generator, and to allow for synchronous clocking of the precharged SRAM. An external clocking method is also provided to directly clock the precharged SRAM. Finally, the self-timing clock generator and the precharged SRAM may be tested through the use of a test enable circuit, which intercepts the generated precharge and clock signals, and provides in place thereof a test precharge and clock signal.

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Eagan, MN, United States of America

Douglas A Fuller