Honeywell G.m.b.h.

Douglas A Fischer

Thomas D Snodgrass

Jennifer A Graves

Glenn M Courtright

Keith L Jackson

Douglas E Thorpe

John F Dawson

Jordon W Woods

Bradley D Peterson

The present invention relates generally to a swimming pool intake filter cover device that is primarily comprised of a generally L-shaped body further comprised of at least one 90-degree elbow, at least one vertical frame member, at least one horizontal frame member, and at least one screen. The body of the device can be placed on a ground surface near a pool and a portion of the body can be placed within the pool in front of the intake filter opening of the skimmer. The portion of the body in front of the filter opening is further comprised of a screen that covers the front and sides of the opening, to prevent debris from entering into the opening. In differing embodiments, the body may be weighted to prevent movement of the body.

Swimming pool intake filter cover device

A parallel polygon/pixel rendering engine for a digital map capable of producing real-time linear shaded, three dimensional, raster graphics for video generation. The apparatus is suitable for use with avionic display systems, particularly digital map displays which include an instruction and interpreter unit and an image scanner. The apparatus comprises a raster engine, a memory interface and a bit mapped memory. The raster engine further includes a raster engine control and generic interpolation polygon processor interface, an edge interpolator, a line interpolator and a controller for the edge and line interpolators. The raster engine control is electrically connected to receive data from the instruction interface unit and is further electrically connected to the edge interpolator and interpolator controller. The edge interpolator is adapted to receive data from the raster engine control and the line interpolator is electrically connected to receive data from the edge interpolator. A first edge pipeline is connected to a second output of the raster engineer control and a second edge pipeline is connected to an output of the first edge pipeline as well as an output of the edge interpolator. An output from the second stage of the edge pipeline and a plurality of outputs from the line interpolators are then fed to a memory interface which is connected to receive data from the plurality of outputs. A bit mapped memory is also connected to receive data from the memory interface and control signals from a bit mapped memory controller. The bit map memory controller controls the memory interface components and the bit map memory during both normal and test modes.

Parallel polygon/pixel rendering engine

A polygon tiling engine for use in a computer graphics display system. The computer graphics display system includes a high speed processor which provides lines of vertices, object type codes and START and STOP points for the vertex lines. The system further includes a VME bus. An improved apparatus for polygon tiling comprises apparatus for receiving the START and STOP points, instruction register apparatus coupled to the high speed processor for receiving instruction codes, object storing apparatus, a state machine for controlling the polygon tiling apparatus, a polygon address generating machine, a user defined object memory, a multiplexer and a triple buffered memory. Information is sent from the high speed processor to the tripled buffered memory, instruction registers and START and STOP registers. The information is processed into polygon addresses by the polygon generating apparatus. The polygon tiling apparatus is capable of tiling terrain data, multivertex polygons and user defined objects. The user defined objects are preferably stored in a link list random access memory. The state machine controls the polygon address generator and receives instructions from the instruction register. User information is supplied on the VME bus. Tiled polygons are output to a polygon sort engine for further processing.

Polygon tiling engine

A polygon sort engine including first and second apparatus for sorting. The first apparatus for sorting receives planar, externally convex polygon vertices from an external polygon tiling engine. This includes points and lines. The state machine on the second apparatus for sorting interfaces with the polygon tiling engine and a raster engine in a graphics pipeline. It provides a control signal which determines when the first apparatus for sorting will receive the next polygon. The second sorting appartus also controls whether the polygon is stored in the PING or PONG memory. For example, as the state machine is controlling the sorting of the current polygon into the PING RAM, the state machine will also be controlling the loading of the previous vertices and the PONG RAM into the raster engine.

Polygon sort engine

A bus interface controller for use in a digital information system. The bus interface comprises more than four bi-directional data channels which are multiplexed so as to accomplish switching of data from any channel to any or all of the remaining channels. The device is preferably embedded in a substate comprising gallium arsenide material and operates at a frequency of at least 25 MHz.

Bus interface controller for computer graphics

A memory interface controller apparatus for use in a digital system, such as a graphics display system. The apparatus comprises apparatus for receiving incoming pixel data and apparatus for detecting pixel address collision. In an alternate embodiment, apparatus for performing hidden surface removal on the incoming pixel data is included. The memory interface controller apparatus further may include apparatus for construction of images with transparent objects.

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Albuquerque, NM, United States of America

Douglas A Fischer