Intel Corporation

Doug Guddat

Jashojiban Banik

Anne Meixner

Glenn F King

A test circuit and method for testing a memory cell in a static random access memory. The memory cell is coupled to a bit line and a complementary bit line. The test circuit includes a charging device coupled to selectively charge one of the bit line or the complementary bit line and a discharging device coupled to selectively discharge the other of the bit line and the complementary bit line. To test a memory cell containing the first value, the test circuit performs a weak write of the second value to the memory cell. The weak write overwrites the first value contained in the memory cell with the second value if the memory cell is defective. The memory cell retains the first value if functioning properly.

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Portland, OR, United States of America

Doug Guddat