Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Beamr Imaging Ltd.

Mealanox Technologies, Ltd.

Dotan David Levi

Natan Manevich

Wojciech Wasko

Ariel Almog

Liron Mula

Lior Narkis

Avi Urman

Bar Shapira

Paraskevas Bakopoulos

Assaf Weissman

Noam Bloch

Avraham Ganor

Ohad Markus

Elad Mentovich

Roee Moyal

Ran Ravid

Thomas Kernen

Aviad Raveh

Ariel Shahar

Idan Burstein

Ioannis (Giannis) Patronas

Dimitrios Syrivelis

Arnon Sattinger

Daniel Marcovitch

Gal Yefet

Shay Aisman

Guy Lederman

Nir Nitzani

Eliel Peretz

Eyal Frishman

Maciek Machnikowski

Michael Kagan

Liran Liss

Gil Bloch

Yuval Itkin

Shie Mannor

Dror Porat

Lavi Koch

Shahaf Shuler

Haggai Eran

Eyal Srebro

Eitan Hirshberg

Chen Gaist

Igor Voks

Aviv Berg

Ariel Naftali Cohen

Amit Mandelbaum

Richard Hastie

Saar Tarnopolsky

Gal Chechik

Kobi Pines

Alex Vainman

Teferet Geula

Ilan Smith

Erez Yaacov

Ofir Sadeh

Jonathan Oliel

Assaf Hallak

Eshed Ram

Uri Gadot

Eitan Zahavi

Dimitrios Kalavrouziotis

Richard Leigh Graham

Hillel Chapman

Tamar Shoham

Boris Pismenny

Dror Gill

Nimer Khazen

Peter Paneah

Ran Avraham Koren

Ran Sela

Gil Kremer

Joseph Boccuzzi

Doron Fael

Maxim Fudim

Tal Anker

Elena Agostini

Roee Shapiro

Dimitris Syrivelis

Artiom Tsur

Reuven Kogan

Eran Ben Elisha

Eyal Serbro

Roi Geuli

Georgi Mihaylov Chalakov

Rafi Weiner

Richard Graham

Sean Pieper

Itai Levy

Alex Vaynman

Shahar Givony

Pavel Titkov

Nikolay Terterov

Alexey Mitkovets

Alexey Martemyanov

Alexander Zheludkov

Oren Matus

Mathias Blake

Shlomi Museri

Minimum processing performed at a signal device level is enabled, such that the majority of the non-domain-specific processing can be offloaded to a processing device. For example, the processing device can receive signal data from a signal device, preprocess the signal data to obtain preprocessed signal data having a data format for domain-specific processing by software executed by at least one processing unit of a processing platform, and provide the preprocessed signal data for domain-specific processing by the software executed by the at least one processing unit.

Software-defined signal device systems

In one embodiment, a system includes a network interface controller to receive a first clock-synchronization message from a clock-synchronization leader device and send a second clock-synchronization messages to at least one clock-synchronization follower device, and a processor to execute software to generate the second clock-synchronization message, and generate a control dependency to condition sending the second clock-synchronization message by the network interface controller to the at least one clock-synchronization follower device on the network interface controller receiving the first clock-synchronization message from the clock-synchronization leader device.

Synchronous clock synchronization messaging

A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

Cross address-space bridging

Approaches in accordance with various embodiments enable communication functionality to be added to an existing hardware component, such as a network interface controller (NIC), data processing unit (DPA), or network switch, rather than requiring an additional component such as a Front Haul Multiplexor (FHM)-type for cellular communications. Such an approach not only avoids the cost and complexity of managing additional hardware components, but can also reduce bandwidth needed for signal transmission. For downlink communications, data can be copied to the relevant radio units of a cell in a single cell deployment architecture to be transmitted to a target client device, such as a cellular handset. For uplink communications, data received from a client device to multiple radio units can undergo decompression and channel estimation before combining the data into a single signal or data stream.

Shared cell support for telecommunications

Apparatuses, systems, and techniques to eliminate redundant data packets. In at least one embodiment, a communication apparatus generates redundant data packets, and sends them in multiple packet streams. In at least one embodiment, a communication apparatus eliminates redundant data packets from received packet streams.

Communication apparatus generating and eliminating redundant data packets

A network interface device includes a local register and packet processing circuitry coupled to the local register. The packet processing circuitry is to: capture a network packet transmitted by a software application running on an integrated computing system; capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities that are running on the integrated computing system; store the receive timestamp in the local register; associate the receive timestamp from the local register with a first packet copy of the network packet; insert the first packet copy to a first receive pipeline of a first subscriber entity; associate the receive timestamp from the local register with a second packet copy of the network packet; and insert the second packet copy to a second receive pipeline of a second subscriber entity.

Precise multicast timestamping

In one embodiment, a processing system includes an interface controller to receive a data signal from a remote link partner over a link, and recover a clock signal from the received data signal, frequency generation circuitry to receive the recovered clock signal, and output a local clock signal responsively to the received recovered clock signal, wherein the interface controller is configured to drive a transmit symbol rate responsively to the local clock signal, and a digital control loop including the interface controller and the frequency generation circuitry, wherein the interface controller is configured to identify a clock drift, generate a digital control signal responsively to the clock drift, and send the digital control signal to the frequency generation circuitry, which is configured to adjust a frequency of the local clock signal responsively to the digital control signal in order to reduce the clock drift.

Hybrid clock synchronization

A system including an acceleration device including input circuitry configured, for each of a first plurality of video frames to be encoded, to receive an input including at least one raw video frame and at least one reference frame, and to divide each of the first plurality of video frames to be encoded into a second plurality of blocks, and similarity computation circuitry configured, for each one of the first plurality of video frame to be encoded: for each block of the second plurality of blocks, to produce a score of result blocks based on similarity of each block in each frame to be encoded to every block of the reference frame, an AC energy coefficient, and a displacement vector. Related apparatus and methods are also provided.

Application acceleration

In one embodiment, a system includes a hardware accelerator to receive video data of multiple video frames, divide each of the video frames into respective blocks, compute encoding assist data including at least one video encoding parameter type for each of the respective blocks of each of the video frames, and store respective portions of the encoding assist data across respective database tables, and an interface to provide the respective database tables to video encoding software running on a processor.

Hardware accelerated video encoding

A system includes a processing device to receive video content, metadata related to the video content, and a target bit rate for encoding the video content. The processing device further detects a content type of the video content based on the metadata and encodes hardware to perform frame encoding on the video content. The system further includes a controller coupled between the processing device and the encoding hardware. The controller is programmed with machine instructions to generate first QP values on a per-frame basis using a frame machine learning model with a first plurality of weights. The first plurality of weights depends at least in part on the content type and the target bit rate. The controller further provides the first QP values to the encoding hardware for rate control of the frame encoding.

Content-aware, machine-learning-based rate control

System, methods, and devices for sharing time information between machines are provided. In one example, a system includes a Precision Time Protocol (PTP) Hardware Clock (PHC) and an application. The application receives time information from the PHC along with contextual metadata associated with the time information, analyzes the contextual metadata associated with the time information, and determines a context in which the PHC is disciplined. The context in which the PHC is disciplined may control a manner in which the application uses the time information.

Companion metadata for precision time protocol (PTP) hardware clock

In one embodiment, a synchronized communication system includes a plurality of network devices, and clock connections to connect the network devices in a closed loop configuration, wherein the network devices are configured to distribute among the network devices a reference clock time from any selected one of the network devices.

Boundary clock synchronized loop

A network adapter includes a host interface and a scheduler. The host interface is configured to receive, from one or more hosts, packets for transmission to respective destinations over a network. The scheduler is configured to synchronize to a time-division schedule that is employed in the network, the time-division schedule specifying (i) multiple time-slots and (ii) multiple respective groups of the destinations that are reachable during the time-slots, and, based on the time-division schedule, to schedule transmission times of the packets to the network on time-slots during which the respective destinations of the packets are reachable.

Time-division multiplexing (TDM) scheduling in a network adapter

In one embodiment, a system includes a digitally controlled oscillator (DCO) to generate a local clock having a local clock frequency, and clock synchronization circuitry to receive from a device a signal indicative of a remote clock frequency, compare measures of the remote clock frequency and the local clock frequency; generate a digital control command based on the comparison; and provide the digital control command to the DCO, wherein the DCO is to adjust the local clock frequency responsively to the digital control command.

Physical layer syntonization using digitally controlled oscillator

In one embodiment, a clock syntonization system includes a first compute node including a first physical hardware clock to operate at a first clock frequency, a second compute node, and an interconnect data bus to transfer data from the first compute node at a data rate indicative of the first clock frequency of the first physical hardware clock, and wherein the second compute node includes clock synchronization circuitry to derive a second clock frequency from the data rate of the transferred data, and provide a clock signal at the derived second clock frequency.

Syntonization through physical layer of interconnects

Growing community of inventors

Kiryat Motzkin, Israel

Dotan David Levi