Lg Display Co., Ltd.

Dosung Kim

Ryosuke Tani

SeYoung Kim

Seonghun Jeong

DaeHyun Nam

Sunyoung Kwon

Sunghak Jo

Seyoung Kim

A display device is proposed, the display device including a display panel in which a plurality of unit pixels composed of n sub-pixels (where n is a natural number of 2 or more) connected to a data line and a gate line are arranged; a data driving circuit sequentially outputting n data voltages through a first output channel for one horizontal period; a latch circuit sequentially sampling the n data voltages input through the first output channel and providing the sampled n data voltages simultaneously to n data lines while maintaining the same for one horizontal period including a first time point at which a n-th data voltage is sampled; and a gate driving circuit supplying a scan signal to the gate line in synchronization with the data voltage supplied to the data line.

Display device

A display device comprises: a panel comprising a pixel array; a data driver for outputting video data signals to the panel; and a latch part for receiving the video data signals from the data driver and outputting the received video data signals to the pixel array. With this configuration, the number of data drive ICs of the data driver can be reduced while maintaining the panel driving frequency.

Display method and method of driving the same

A display device for preventing a defective drive and improving reliability is disclosed. The display device includes a substrate including a display portion and a pad portion outside the display portion, a plurality of power lines positioned on the pad portion of the substrate and extended from the display portion, a plurality of data lines positioned in parallel with the plurality of power lines and extended from the display portion, and a plurality of bridge electrodes configured to connect at least two of the plurality of power lines. Some of the plurality of power lines include a power pad electrode on at least an end of the corresponding power line, and a number of the power pad electrodes is less than a number of the power lines.

An organic light emitting diode display includes a substrate; a buffer layer on the substrate; a scan line running to a horizontal direction on the buffer layer; an intermediate insulating layer covering the scan line; a first trench having a segment shape apart from the scan line with a predetermined distance and exposing some of the substrate by patterning the intermediate insulating layer and the buffer layer; a data line running to a vertical direction on the substrate exposed by the first trench and on the intermediate insulating layer; a passivation layer covering the data line and the scan line; and a color filter filling into the trench and depositing on the passivation layer.

Organic light emitting diode display capable of reducing RC load

The present disclosure relates to a display having a narrow bezel structure. A flat panel display includes a substrate including a display area and a non-display area; a pull-up thin film transistor including a first gate electrode, a first source electrode and a first drain electrode, disposed in the non-display area; and a boosting capacitor disposed between the first gate electrode and the first source electrode; wherein the boosting capacitor includes a light shielding layer connected to the first gate electrode and overlapping with the first source electrode, but not overlapping with the first drain electrode.

Display having narrow bezel

Embodiments of the invention relate to a stereoscopic image display and a method for driving the same. Stereoscopic image display includes a data display unit including a first scan transistor, an active black stripe unit including a second transistor and a third transistor, and a shift register sequentially supplying the gate pulse to each of (2n&#x2212;1)th gate lines and (2n)th gate lines, where n is a natural number. The first scan transistor supplies a data voltage to a pixel electrode in response to a gate pulse of a (2n&#x2212;1)th gate line, the second transistor supplies the data voltage to the pixel electrode in response to the gate pulse of the (2n&#x2212;1)th gate line, and the third transistor supplies a low logic level voltage or a common voltage to the pixel electrode in response to a gate pulse of a (2n)th gate line.

Growing community of inventors

Paju-si, South Korea

Dosung Kim