Cisco Technology, Inc.

Infineon Technologies North America Corp.

Doron Shoham

Shimon Listman

Rami Zemach

John Joseph Williams, Jr

Amir Michaeli

Sarig Livne

Ilan Lisha

Earl T Cohen

Chandrashekhar Appanna

John Andrew Fingerhut

David J Tsiang

Alon Ratinsky

Sivan Avraham

Gilad Hazan

Robert C Olsen

Anna Charny

John H W Bettink

Eyal Oren

Christopher J Kappler

Yannick Martelloni

Moshe Voloshin

Gigy Baror

Dalit Sagi

Klaus J Oberlaender

Niv Margalit

Sabeen Randhawa

John J Williams

Aravinth Nagamani Manickam

Eliahu Shapiro

Ehud Finkelstein

Yossi Socoletzky

Manfred Henftling

Zohar Peleg

Oded Trainin

Christian Wiedholz

David Tsiang

In one embodiment, content-addressable memory lookup result integrity checking and correcting operations are performed, such as, but not limited to protecting the accuracy of packet processing operations. A lookup operation is performed in the content-addressable memory entries based on a lookup word resulting in one or more match vectors. One or multiple result match vectors are produced, depending on whether each of the content-addressable memory entries and the lookup word have been partitioned into multiple portions. An error accuracy code (e.g., error detection, error correction) is acquired for each portion of the one or multiple portions based on a corresponding portion of the lookup word. An accurate result is generated by processing each of the result match vector(s) with their corresponding error accuracy code. When using multiple portions, the (possibly corrected) result match vectors are combined into a single accurate result match vector.

Efficient content-addressable memory lookup result integrity checking and correcting operations including for protecting the accuracy of packet processing operations

In one embodiment, updating and searching of entries in a hardware content-addressable memory is coordinated to provide more searching bandwidth (e.g., for determining packet processing information), including, but not limited to, when vectors are moved among entries to free up desired entry positions for insertion of other vectors. A lookup operation is performed in content-addressable memory entries in a hardware content-addressable memory based on a lookup word to generate a content-addressable memory lookup result. Typically overlapping in time, a matching operation is performed in one or more transitory entries to generate a transitory matching result based on the lookup word. These transitory entries are populated with transitory vectors and have an associated index within the content-addressable memory, with these transitory vectors are subsequently inserted in the content-addressable memory at their associated index positions. A matching result is determined from the content-addressable memory lookup result and the transitory matching result.

Coordinated updating and searching a content-addressable memory including for packet processing operations

In one embodiment, efficient content-addressable memory entry integrity checking is performed that protects the accuracy of lookup operations. Single-bit position lookup operations are performed resulting in match vectors that include a match result for each of the content-addressable memory entries at the single-bit position. An error detection value is determined for the match vector, and compared to a predetermined detection code for the single-bit position to identify whether an error is detected in at least one of the content-addressable memory entries. In one embodiment, a particular cumulative entry error detection vector storing entry error detection information for each of the content-addressable memory entries is updated based on the match vector. The particular cumulative entry error detection vector is compared to a predetermined entry error detection vector to determine which, if any, of the content-addressable memory entries has an identifiable error, which is then corrected.

Efficient content-addressable memory entry integrity checking including for protecting the accuracy of packet processing operations

In one embodiment, error detection and correction is performed in a content-addressable memory using single-bit position lookup operations. A lookup operation is performed generating a resultant match vector reflective of matching a single-bit position within each of multiple content-addressable memory entries against a corresponding bit value at the single-bit position within a lookup word. The resultant match vector is processed to determine if there are any errors and typically which entries contain a wrong bit value. The correct match vector (e.g., having no errors) is determined from the correct stored matching values (e.g., those used to program the content-addressable memory entries) and the value at the single-bit position within the lookup word. One embodiment compares the correct and resultant match vectors, while one embodiment performs this comparison using an error-correcting code of the correct match vector.

Error detection and correction in a content-addressable memory using single-bit position lookup operations

In one embodiment, a content-addressable memory has multiple blocks of content-addressable memory entries, including different first and second sets of content-addressable memory blocks. One embodiment determines the first set of content-addressable memory blocks based on a content-addressable memory profile identifier and a search key and then performs a first content-addressable memory lookup operation in each of the first set of content-addressable memory blocks, but not in the second set of content-addressable memory blocks, based on the search key. If at least one entry is match, a corresponding result is identified. Otherwise, in one embodiment, the second set of content-addressable memory blocks is determined based on the content-addressable memory profile identifier but not based on the search key, and a search is made therein to identify a matching result or that no match was determined. In one embodiment, a matching result determines how a packet is processed.

Searching varying selectable physical blocks of entries within a content-addressable memory

In one embodiment, packets are forwarded in a network based on lookup results in a content-addressable memory that includes multiple blocks of content-addressable memory entries, with the relative priority of these blocks typically determined on a per search basis. In one embodiment, the content-addressable memory blocks perform lookup operations based on a search key resulting in a lookup results. The result determiner determines an overall highest-priority content-addressable memory lookup result based on ordering the lookup results according to a dynamic priority ordering (e.g., retrieved from storage) among the content-addressable memory blocks. One embodiment allows multiple searches to occur simultaneously among the content-addressable memory blocks by selectively performing lookup operations on multiple search keys. One embodiment weights such lookup operations to initially assign search keys to content-addressable memory block(s) with a corresponding higher-priority, and if a match is found, other content-addressable memory block(s) will not need to be searched.

Dynamic priority of content-addressable memory blocks used in determining a highest-priority matching entry

In one embodiment, an associative memory is built using multiple cascaded associative memory blocks, with stored lookup words spanning a same or different numbers of associative memory blocks. A first lookup operation is performed by a first associative memory to generate first matching indications of associative entries of the first associative memory that match both the first lookup word and the first lookup type. A second lookup operation is performed by an end associative memory to generate end matching indications of associative entries of the end associative memory that match both the end lookup word and the end of word lookup type. A final lookup result indicating a matching multi-block spanning associative memory entry based on the first matching indications and the end matching indications is determined and signaled by the associative memory is built using multiple cascaded associative memory blocks.

Associative memory including multiple cascaded associative memory blocks and its use in forwarding packets in a network

In one embodiment, individual or groups of heat generating data processing operations are rate-controlled such that a component, a set of components, a board or line card, and/or an entire apparatus or any portion thereof stays within a corresponding heat budget. One or more heat price tags are associated with these data processing operations which are used to determine whether or not a corresponding data processing operation can be currently performed within one or more corresponding heat budgets. If so, the data procession operation proceeds. If not, the data processing operation is delayed. Examples of such data processing operations include, but are not limited to, data retrieval from memory, data storage in memory, lookup operations in memory, lookup operations in a binary or ternary content-addressable memory, regular expression processing, cryptographic processing, or data manipulation.

Rate-controlling of heat generating data processing operations

In one embodiment, packets are sent a packet switching mechanism of a packet switching device, which includes partitioning each particular packet into a plurality of cells with each particular packet and cell derived therefrom associated with a same particular timestamp and a same particular ingress point identifier representing an ingress point of a plurality of ingress points of the packet switching mechanism. These cells are sent through the packet switching mechanism by selecting and forwarding, at each of a plurality of points within the packet switching mechanism. A tie-breaking value is determined based on a manipulation of ingress point identifier associated with said identifiable cell in a manner to vary the tie-breaking selection ordering of ingress point identifiers for different timestamp values. The tie-breaking value is used in selecting a next cell to forward when cells are associated with a same timestamp.

Cell forwarding order selection for sending packets

In one embodiment, batch entries include multiple content-addressable memory (CAM) entries, and CAM entries are allowed to be shared among different batch entries. For example, two or more batch entries might have a common set of bits (e.g., representing an address, an address prefix, etc.). Rather than consuming bits of multiple CAM entries, a single CAM entry can be programmed with this common information. Other CAM entries associated with different batch entries are programmed with the distinguishing/different values. A batch lookup operation on a batch entry of two or more CAM entries requires multiple lookup operations on the CAM entries. One embodiment uses a batch mask vector to provide information to decode what CAM entries are shared among which batch entries during a series of lookup operations, which can be performed in one or both directions through the CAM entries.

Batch entries sharing individual content-addressable memory entries

In one embodiment, multiple content-addressable memory entries are associated with each other to effectively form a batch content-addressable memory entry that spans multiple physical entries of the content-addressable memory device. To match against this content-addressable memory entry, multiple lookup operations are required&#x2014;i.e., one lookup operation for each combined physical entry. Further, one embodiment provides that a batch content-addressable memory entry can span one, two, three, or more physical content-addressable memory entries, and batch content-addressable memory entries of varying sizes could be programmed into a single content-addressable memory device. Thus, a lookup operation might take two lookup iterations on the physical entries of the content-addressable memory device, with a next lookup operation taking a different number of lookup iterations (e.g., one, three or more).

Content-addressable memory lookup device supporting iterative lookup operations

Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for filling token buckets of schedule entries, such as those used in, but not limited to, a scheduling system used in a computer or communications system (e.g., for sending packets, allocating processing resources, etc.). A scheduling system includes multiple schedule entries with a number of tokens and a last filled slot value. A period of time allocated for periodically updating the number of tokens for all of the schedule entries is divided into the slots, and each schedule entry is associated with a particular fill slot. Each particular schedule entry is repeatedly sequence through and updated during is corresponding slot; while in parallel, a next schedule entry to service is repeatedly identified and updated, while in parallel, ineligible entries schedule to be woken up for the current time slot are made eligible.

Filling token buckets of schedule entries

A method for communication includes allocating target bandwidths to two or more packet sources and defining one or more of the packet sources as preferred sources. Quantum values defining maximum amounts of data to be sent during a single scheduling round are defined for the respective packet sources. Repetitive scheduling rounds are performed in order to determine a schedule for processing pending data packets produced by the packet sources. In each scheduling round, all pending packets that are produced by the preferred sources and are within the target bandwidths allocated to the preferred sources are scheduled. Pending packets produced by packet sources other than the preferred sources are scheduled in accordance with the quantum values, within the target bandwidths allocated to the packet sources other than the preferred sources. The pending packets are processed responsively to the schedule. The target bandwidths may comprise, for example, guaranteed bandwidths or excess bandwidths.

Oversubscription of guaranteed bandwidth

Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is typically performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.

Distributed packet processing with ordered locks to maintain requisite packet orderings

A method for controlling data transmission includes setting a respective rate criterion for each of a plurality of interfaces of a network element. Upon conveying a first data packet of a first size via a given interface of the network element at a first time, a time-stamp value is computed based on the first time, the first size and the respective rate criterion that is set for the given interface. A disposition of a second packet for conveyance via the given interface at a second time, subsequent to the first time, is determined responsively to the time-stamp value.

Growing community of inventors

Shoham, Israel

Doron Shoham