Intel Corporation

Apple Inc.

Daedalus Prime LLC

Bandwiz Inc.

Tahoe Research, Ltd.

Daedauls Prime LLC

Doron Rajwan

Efraim Rotem

Eliezer Weissmann

Nadav Shulman

Avinash N Ananthakrishnan

Nir Rosenzweig

Ryan Donovan Wells

Alon Naveh

Inder M Sodhi

Yoni Aizik

Tal Kuzi

Dorit Shapira

Itai Feit

Tomer Ziv

Eric C Samson

Zeev Offen

Hisham Abu Salah

Hisham Abu-Salah

Guy M Therien

Lior Zimet

Gal Leibovich

Esfir Natanzon

Yevgeni Sabin

Alexander Gendler

James G Hermerding, Ii

Eric DiStefano

Ishmael F Santos

Jeffrey A Carlson

Keith Alan Cox

Jeremy J Shrall

Lev Finkelstein

Kosta Luria

Arik Gihon

Ido Melamed

Ronny Korner

Karl Daniel Wulcan

Hong Jiang

Paul S Diefenbaugh

Barnes Cooper

Ronny Ronen

Ron Gabor

Russell Jerome Fenger

Dean A Mulla

Dan Baum

Michael Mishaeli

Luca O Iuliano

Ilya Granovsky

Jorge Pedro Rodriguez

Jung Wook Cho

Yuval Yosef

Jamie L Langlinais

Ali Rabbani Rankouhi

Lital Levy-Rubin

Philip R Lehwalder

Ariel Szapiro

Craig S Forbell

Ariel Gur

Aviad Cohen

James Varga

Ami Schwartzman

Nir Tell

Gady Yearim

Niv Tokman

Bart Plackle

Shay Levy

Amit Gabai

Eliezer Wiessman

Kevin I Park

Ankush Varma

Tod F Schiff

Ahmad Yasin

Achmed Rumi Zahir

Alexander Uan-Zo-Li

Lily Pao Looi

Michael Zelikson

Yizhang Yang

Sagi Lahav

Daniel U Becker

Israel Hirsh

Joseph Yossi Azar

Nir Leshem

Omer Vikinski

Maxim Levit

Eyal Lubetzky

Shmuel Zobel

David Pawlowski

Gary A Andrew

Jeffrey Jull

Avinash N Ananthakrishan

Natanel Abitan

Assaf Ganor

Eliezer Wiessmann

Yossi Abulafia

Rotem Efraim

Saher Odeh

Maytal Toledano

Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

Quality-of-service-based fabric power management

In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Multi-level loops for computer processor control

In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

Processor having accelerated user responsiveness in constrained environment

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Controlling operating voltage of a processor

An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits. The control circuitry controls the voltage regulators to supply the adjustable operating voltages responsively to requests from the hardware circuits, compares the adjustable operating voltages to settings that are specified as safe for provisioning by a predefined partial number of the power stages of the front-end power supply, and adaptively activates and deactivates the power stages, including ensuring that a number of active power stages is set to the predefined partial number only while the operating voltages match the safe settings.

System-on-chip with power supply mode having reduced number of phases

A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

System, apparatus and method for loose lock-step redundancy power management

A system includes multiple hardware circuits and protection circuitry. The multiple hardware circuits are coupled to respective power domains having respective sets of domain-specific power settings. The protection circuitry is configured to monitor requests in which one or more of the hardware circuits request transitions between the domain-specific power settings, to determine, from among multiple system-level combinations of the domain-specific power settings, a subset of system-level combinations that could potentially be traversed in performing the requested transitions, and to initiate a responsive action upon detecting that any of the system-level combinations in the subset is specified as invalid.

System-on-chip with DVFM protection circuit

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Request and floor interface for current control with correctness in an SOC

Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.

Telemetry push aggregation

Global integrated circuit power control

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).

Power management based on limiting hardware-forced power control

An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

Power consumption control based on random bus inversion

Controlling operating frequency of a processor

Growing community of inventors

Rishon Le-Zion, Israel

Doron Rajwan