Cadence Design Systems, Inc.

Doron Bustan

Habeeb Farah

Karam Abdelkader

Yaron Schiller

Thiago Radicchi Roque

Nizar Hanna

Almothana Sarhan

Felipe Althoff

Ayman Hanna

Karam Abd Elkader

Method includes, for a point in MCP circuit, performing backward traversal of the circuit along the COI of that point, to sequential elements directly driving that point; constructing a counter circuit for all sequential elements driving that point, and combining the constructed counter circuits to a combined logical circuit of all of the counters in the COI, to determine whether signals in the COI are stable; performing a fan out traversal of the MCP circuit from the selected point and up to next immediate sequential elements downstream in the fan out; constructing a combinational logic circuit for the combinational elements in the fan out to determine whether that combinational element blocks a signal of the signal paths when that signal is unstable, and combining the combinational logic circuits to a combined combinational logic circuit; and checking an assertion that inputs of the next immediate sequential elements are stable.

System and method for formal verification of a multi-cycle path circuit

A method for enhancing performance of SEC of two representations of an electronic design (with and without gated clock) includes selecting one or more pairs of correlated flip-flops (FFs), a first FF of each pair in the first representation toggled by the gated clock controlled by an enable combinational logic and a second FF of the pair, correlating to the first FF, in the second representation toggled by the constantly toggling clock. The method also includes defining a modified enable combinational logic for the gated clock, as a disjunction of the enable combinational logic of the gated clock and an enable combinational logic for each FF of a plurality of FFs that are toggled by the gated clock. The method also includes performing SEC on the two representations design, using the modified enable combinational logic for the gated clock instead of the enable combinational logic of the gated clock.

Method and system for sequential equivalence checking

A method for sequential equivalence checking (SEC) of two representations of an electronic design may include using a processor, automatically selecting a plurality of cutpoints in the two representations of the electronic design; using a processor, automatically executing a prove-from strategy on the plurality of cut point pairs to identify a failed cut point pair in the two electronic designs; and using the processor, automatically extending a trace corresponding to the identified failed cut point pair to identify a deeper failed cut point pair or a failed output pair in the two electronic designs.

The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of flip-flops from the plurality of flip-flops and disabling a second clock associated with the second set of flip-flops without changing a value of the second set of flip-flops. Embodiments may further include determining whether a first output from the first set of flip-flops and a second output from the second set of flip-flops have converged.

System, method, and computer program product for clock gating in a formal verification

The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include providing, using at least one processor, an electronic design and performing formal verification of at least a portion of the electronic design having an original property. Embodiments may further include analyzing at least one output net bit associated with a check of the electronic design. Embodiments may also include generating a structural observability expression, based upon, at least in part, the at least one output net bit and setting the structural observability expression as a precondition to the original property.

Growing community of inventors

Zichron Yaakov, Israel

Doron Bustan