Rca Inc.

General Electric Company

United States of America As Represented by the Secretary of the Air Force

Harris Corporation

Doris W Flatley

Sheng T Hsu

Alfred C Ipri

Kenneth M Schlesier

Ronald J Johansson

A structure and method for making a pair of MOS field effect transistors (MOSFETs), one stacked upon the other in an integrated circuit device is disclosed. In one embodiment of the device, the active layer of the upper MOSFET is epitaxially grown from an exposed surface of the active layer of the lower MOSFET. In another embodiment, the active layer of the upper MOSFET is polysilicon which, optionally, may be recrystallized. In all embodiments, the pair of MOSFETs share a common gate.

Integrated circuit with stacked MOS field effect transistors

A method of making a MOS transistor having source and drain extensions includes forming on a surface of a substrate of single crystalline silicon a gate line having a thin layer of silicon oxide between the gate line and the substrate surface. A light dose of ions of a desired conductivity type are embedded in the substrate surface at each side of the gate line up to the side walls of the gate line. Spacers of thermally grown silicon oxide are formed on the side walls of the gate line and a dose of the ions of the desired conductivity type are embedded into the substrate surface at each side of the gate line to form source and drain regions. The source and drain regions extend up to the spacers and have lightly doped extensions extending up to the side walls of the gate line under the spacers.

Method of making a MOS transistor

A process for forming a silicon-on-sapphire integrated circuit comprises forming a layer of a conformal dielectric material, such as silicon dioxide, over a sapphire substrate having at least one island of silicon on a major surface thereof; forming a layer of a planarizing material over the dielectric layer, anisotropically etching the planarizing material for a time sufficient to expose the surface of the dielectric layer overlying the island; etching the dielectric layer for a time sufficient to expose at least the top surface of the island; removing the remaining planarizing material, growing a thin layer of gate oxide on the exposed surface of the island and providing a patterned layer of conductive polycrystalline silicon thereover. The etching of the dielectric layer can be continued to at least partially expose the sidewall surface of the islands. Preferably, etching is continued for a time sufficient to completely expose the sidewall surfaces of the isla

Silicon-on-sapphire integrated circuits

A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. The layer of silicon is oxidized and the oxide layer is anisotropically etched until the top surface of the island is exposed, leaving oxide only on the sidewalls of the island. The exposed portion of the island is then oxidized to form a thin layer of gate oxide thereon. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

Method of forming a semiconductor structure

A semiconductor device includes a substrate of single crystalline silicon having the active regions of a semiconductor element, such as the source, drain, channel and gates, along one surface of the substrate, and a thin gettering region of a gettering material in the substrate. The gettering region is spaced from both surfaces of the substrate and is adjacent the active regions of the semiconductor element so as to getter contaminants in the substrate from the area of the substrate containing the semiconductor element.

Semiconductor device with internal gettering region

A multi-level metallization is formed by forming a patterned first level metallization layer on the surface of an isolating layer on a substrate of semiconductor material. A thick planarizing layer, preferably of a glass, is applied over the first level metallization layer and the exposed areas of the insulating layer with the planarizing layer bearing depressions in its surface over the exposed areas of the insulating layer. A photoresist layer is formed on the planarizing layer in the depressions in its surface with the portions of the planarizing layer over the first level metallization layer being exposed. The exposed areas of the planarizing layer are isotropically etched until the surface of the planarizing layer is substantially planar with the bottom of the deepest depression in the planarizing layer. Any photoresist material is removed and the planarizing layer is isotropically etched until its surface is substantially planar with the surface of the first level metallization layer. An inter-level insulating layer is applied over the planarized surfaces of the first level metallization layer at the planarizing layer, and a second level metallization layer is applied over the inter-level insulating layer.

Method of forming multi-level metallization

A method for forming a layer of silicon dioxide over a silicon island on an insulating surface wherein the layer on top of the island is thinner than on the sidewalls is disclosed. The silicon island is oxidized and a silicon layer is deposited thereover. A layer of planarizing material is deposited over the silicon layer. The planarizing layer is anisotropically etched until the surface of the silicon layer overlying the island is exposed. The silicon layer is in turn etched until the surface of the oxide layer overlying the island is exposed. The remaining planarizing material is removed and the remaining silicon layer is oxidized. The thickness of the gate oxide layer on top of the island may be controlled by again exposing the island surface and reoxidizing to a predetermined thickness. A conductive polycrystalline silicon electrode is deposited on the oxide-covered island. The disclosed method is particularly useful in the formation of MOSFETs.

The ion implantation of a silicon structure isolated from a semiconductor substrate by a layer of silicon dioxide with boron ions to render it p type conductive is improved by initially doping the silicon with phosphorus ions. The presence of the phosphorus ions in the silicon prevents the implanted boron ions from rapidly migrating into the silicon dioxide during annealing.

Profile control of boron implant

A process for defining improved tapered openings in glass coatings requires that passivating layers be formed of a doped silicon oxide having a relatively low flow temperature formed on a layer of undoped silicon oxide. After the contact openings are formed, both oxide layers are heated to a temperature below the flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer, the temperature being insufficient to form a significant oxide growth on the exposed portion of the semiconductor body.

Process for tapering openings in ternary glass coatings

The radiation resistance of an MOS transistor is improved by making the transistor in a manner such that, after the gate insulation layer is formed, all further steps are carried out at a relatively low temperature, i.e., less than about 900.degree. C. The source and drain regions are preferably formed by ion implantation with very little or no post implant thermal activation, and the metallization is applied by low temperature techniques.

Method of making radiation resistant MOS transistor

An improved process of forming planar silicon-on-sapphire MOS integrated circuit devices by a local oxidation process in which portions of a silicon layer on a sapphire substrate are thermally oxidized throughout the thickness of the layer to provide interdevice dielectric isolation and a substantially planar topology includes a step of ion implanting phosphorus, boron, or a combination thereof into the silicon prior to the thermal oxidation step. The implanted impurities have a stabilizing effect on the devices thereafter built in the remaining silicon.

Process of making a planar MOS silicon-on-insulating substrate device

A semiconductor structure from which various types of active semiconductor devices can be formed is made of a semiconductor island on a transparent substrate, having thereon an electrically insulating layer of a protective material, such as silicon dioxide, which extends onto and covers the sides of the semiconductor island. The protective layer can either cover only the sides of the semiconductor island or extend over the top edge of the island. The protective layer is made by etching through a photoresist mask made of a negatively reacting photoresist which is formed by exposure to irradiation from beneath the uncovered surface of the substrate, whereby the thickness of the silicon island and the flux density of the irradiation are selected so that for a particular duration, the irradiation is completely attenuated by the semiconductor island.

Method for making semiconductor structure

MNOS memory circuit fabrication problems that result in leakage, memory device depletion mode switching and leakage paths at the edges of silicon islands are eliminated by a production process in which deposited and thermal oxides are used as a diffusion mask on the island edges, selective control of the threshold level of the memory device is achieved by ion implantation, and a thick oxide is grown on the silicon island edges to control charge injection.

Growing community of inventors

Belle Mead, NJ, United States of America

Doris W Flatley