Samsung Electronics Co., Ltd.

Doowon Kwon

Donghyun Kim

Ingyu Baek

Seung-Hun Shin

Jinyoung Kim

JungChak Ahn

Dongchan Kim

Changrok Moon

Minho Jang

Ho-chul Ji

Taeseok Oh

Kwansik Cho

Seokjin Kwon

Kyungrae Byun

Jameyung Kim

Bokwon Kim

Mangeun Cho

Hyunyoung Yeo

In Ho Ro

Kyungtae Lim

Sungki Min

Provided is an image sensor including a first layer including a first semiconductor substrate including a pixel unit in which a plurality of unit pixels are provided, and a first wiring layer provided on the first semiconductor substrate, a second layer including a second semiconductor substrate on which a plurality of transistors configured to operate a global shutter operation are provided, and a second wiring layer provided on the second semiconductor substrate, and provided on the first layer such that the first wiring layer and the second wiring layer oppose each other in a first direction, a plurality of first bonding structures bonding the first layer to the second layer based on a first bonding metal exposed on a surface of the first wiring layer being in contact with a second bonding metal exposed on a surface of the second wiring layer, a third layer including a third semiconductor substrate on which a logic circuit is provided, and a third wiring layer provided on the third semiconductor substrate, and bonded to the second layer such that the second semiconductor substrate and the third wiring layer oppose each other in the first direction, and a plurality of second bonding structures extending from the second wiring layer, and bonding the second layer to the third layer based on a bonding via penetrating the second semiconductor substrate being in contact with a third bonding metal exposed to a surface of the third wiring layer.

Image sensor and method of manufacturing the same

An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.

Image sensor chip

An image sensor includes a first layer including pixels in a pixel array, and a first logic circuit configured to control the pixel array. Each of the pixels include at least one photodiode configured to generate a charge in response to light, and a pixel circuit configured to generate a pixel signal corresponding to the charge. A second layer includes a second logic circuit that is connected to the pixel array and the first logic circuit and is on the first layer. A third layer includes storage elements that are electrically connected to at least one of the pixels or the first logic circuit and an insulating layer on the storage elements. A lower surface of the insulating layer is attached to an upper portion of the first layer, and an upper surface of the insulating layer is attached to a lower portion of the second layer.

Image sensor and manufacturing method of the same

An image sensor is provided. The image sensor includes a first substrate; a plurality of photoelectric conversion units positioned in the first substrate; a first connection layer disposed on the first substrate; a plurality of first pixel pads disposed on the first connection layer; a plurality of first peripheral pads disposed on the first substrate; a plurality of second pixel pads respectively positioned on the plurality of first pixel pads; a plurality of second peripheral pads respectively positioned on the plurality of first peripheral pads; a second connection layer disposed on the plurality of second pixel pads and the plurality of second peripheral pads; a device disposed on the second connection layer; and a second substrate disposed on the second connection layer and the device, wherein a pitch of the plurality of first pixel pads is substantially the same as a pitch of the plurality of pixel regions of the first substrate.

Image sensor

An image sensor including a semiconductor substrate having a first surface and a second surface, and a pixel region having a photoelectric conversion region; a first conductive pattern in a first trench defining the pixel region and extending from the first surface toward the second surface; a second conductive pattern in a second trench shallower than the first trench and defined between a plurality of active patterns on the first surface of the pixel region; a transfer transistor and a plurality of logic transistors on the active patterns; and a conductive line on the second surface and electrically connected to the first conductive pattern.

Disclosed is an image sensor comprising a first substrate including a plurality of pixels, a photoelectric conversion region in the first substrate at each of the pixels, a first capacitor on the first substrate, and a shield structure spaced apart from and surrounding the first capacitor.

Image sensor including a shield structure

A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.

Semiconductor devices including stacked semiconductor chips

A stack-type semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower interconnection on the lower substrate, a lower pad on the lower interconnection, and a lower interlayer insulating layer covering side surfaces of the lower interconnection and the lower pad. The upper device includes an upper substrate, an upper interconnection under the upper substrate, an upper pad under the upper interconnection, and an upper interlayer insulating layer covering side surfaces of the upper interconnection and the upper pad. Each of the pads has a thick portion and a thin portion. The thin portions of the pads are bonded to each other, the thick portion of the lower pad contacts the bottom of the upper interlayer insulating layer, and the thick portion of the upper pad contacts the top of the lower interlayer insulating layer.

Stack-type semiconductor device

A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.

Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same

An image sensor includes a pixel array chip, a logic chip, and an interposed layer. The interposed layer is disposed on the pixel array chip. The logic chip is disposed on the interposed layer. The interposed layer includes a connecting part, a shielding part, and a metal-diffusion barrier layer. The connecting part electrically connects a first interconnection wire of the pixel array chip and a second interconnection wire of the logic chip. The connecting part includes a first metallic element. The shielding part is disposed spatially apart from the connecting part and electrically grounded to suppress an electrical coupling between the pixel array chip and the logic chip. The shielding part includes a second metallic element. The metal-diffusion barrier layer is disposed on top and bottom surfaces of the interposed layer to limit diffusion of electrical charges to the pixel array chip and the logic chip.

Image sensors include a pixel region and a logic region. Pixel isolation regions in the pixel region include pixel isolation region walls that are less sloped than logic isolation region walls in the logic region. An impurity layer also may be provided adjacent at least some of the pixel isolation region walls, wherein at least some of the logic isolation region walls are free of the impurity layer. The impurity layer and/or the less sloped logic isolation region walls may also be provided for NMOS devices in the logic region but not for PMOS devices in the logic region. Doped sacrificial layers may be used to fabricate the impurity layer.

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Seongnam-si, South Korea

Doowon Kwon