Samsung Electronics Co., Ltd.

Doohee Hwang

Myunghun Woo

Minkyung Bae

Taehun Kim

Bongyong Lee

Yeonkyu Choi

Jooheon Kang

Yukio Hayakawa

Dokyun Kim

Gunwook Yoon

Tae Hun Kim

Seungwoo Ryu

Kwanghyun Kim

Jeongseok Seo

Saemi Song

Nayeong Yun

Chikook Kim

Seongjin Lee

A vertical non-volatile memory device includes: a memory stack structure including gate lines and interlayer insulating layers and a channel hole extending in a stacking direction; a channel layer in the channel hole and extending in the stacking direction; and an information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer, wherein the composite blocking insulating layer includes a metal oxide having a higher dielectric constant than silicon oxide, and the composite blocking insulating layer includes a first blocking insulating layer on sides of the gate lines and a second blocking insulating layer that is between the first blocking insulating layer and the charge storage layer and has a lower oxidation density than the first blocking insulating layer.

Vertical non-volatile memory devices

A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

Vertical variable resistance memory devices and methods of operation in the same

Provided are a memory device and a method of refreshing the memory device regardless of a refresh rate multiplier for a temperature. In response to a refresh command at each base refresh rate (tREFi) based on a measured temperature, a memory device refreshes M memory cell rows at room temperature, refreshes 2M memory cell rows at a high temperature, and refreshes (&#xbd;)M memory cell rows at a low temperature. The memory device refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a refresh command applied after n skipped base refresh rates, and refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a pulling-in refresh command.

Memory device and method of refreshing memory device based on temperature

A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

Method of fabricating a vertical semiconductor device

A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.

Memory system performing hammer refresh operation and method of controlling refresh of memory device

A semiconductor memory device includes an external resistor provided on a board and a plurality of memory dies mounted on the board, designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation during an initialization sequence of the semiconductor memory device and stores, in a first register set therein, first calibration data, a first voltage and a first temperature. Each of the slave dies, after the first impedance calibration operation is completed, performs a second impedance calibration operation during the initialization sequence and stores, in a second register set therein, second calibration data associated with the second impedance calibration operation and offset data corresponding to a difference between the first calibration data and the second calibration data.

Semiconductor memory devices and memory systems including the same

Vertical semiconductor device and method of fabricating the same

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same

An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

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Uiwang-si, South Korea

Doohee Hwang