Samsung Electronics Co., Ltd.

Doo-Young Lee

Do-hyoung Kim

Heungsik Park

Jong-chul Park

Sang-sup Jeong

Jin-Young Kim

Sang-hyun Lee

Dohyoung Kim

Yoonhae Kim

Hwichan Jun

Myung-Hoon Jung

Chulsung Kim

Ki-jin Park

Hyoseok Choi

Johnsoo Kim

Sanghyun Lee

Myeong-Cheol Kim

Nam-Gun Kim

Ki Il Kim

Sung-Il Cho

Keunhee Bai

Hongsik Shin

Yoo-Chul Kong

Yoon-Jae Kim

Hong-sik Shin

Sung-Gil Choi

Hyon-wook Ra

Seo-bum Lee

Sung-gil Choi

Won-hyuk Lee

Younghun Choi

Do-Hsing Lee

Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

Semiconductor device

Provided is a semiconductor device having an enhanced characteristic and a resistor structure satisfying a desired target resistor value of a resistor device. A semiconductor device includes: a lower interlayer insulating layer disposed on a substrate comprising a resistor area; a resistor structure comprising a resistor layer and an etch stop pattern sequentially stacked on the lower interlayer insulating layer of the resistor area; an upper interlayer insulating layer configured to cover the resistor structure and disposed on the lower interlayer insulating layer; a resistor contact structure configured to pass through the upper interlayer insulating layer and the etch stop pattern and contact the resistor layer; and a resistor contact spacer disposed between the upper interlayer insulating layer, the etch stop pattern, and the resistor contact structure.

Semiconductor device including resistor structure

Semiconductor device with field effect transistors and method of fabricating the same

A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

Semiconductor device and method for fabricating the same

A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

Methods of forming semiconductor device

A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Methods of manufacturing semiconductor devices including gate patterns with sidewall spacers and capping patterns on the sidewall spacers

A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.

Method of manufacturing semiconductor devices

A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.

Method of fabricating semiconductor device

Methods of forming integrated circuit devices include upper sidewall spacers in contact holes to provide enhanced electrical isolation to contact plugs therein while maintaining relatively low contact resistance. These methods include forming an interlayer insulating layer on a semiconductor substrate. The interlayer insulating layer includes at least a first electrically insulating layer of a first material on the semiconductor substrate and a second electrically insulating layer of a second material on the first electrically insulating layer. A contact hole is formed that extends through the interlayer insulating layer and exposes a primary surface of the semiconductor substrate. This contact hole may be formed by selectively etching the second electrically insulating layer and the first electrically insulating layer in sequence and at a faster etch rate of the first material relative to the second material. This sequential etching of the first material at a faster rate than the second material may yield a contact hole having a recessed sidewall.

Methods of forming integrated circuit devices using contact hole spacers to improve contact isolation

A semiconductor device includes a word line structure that extends in a first direction on an active region defined on a substrate. First and second contact pads are formed on the active region at both sides of the word line structure. Bit line structures are electrically connected to the first contact pad and extend in a second direction substantially perpendicular to the first direction. An insulation layer structure is formed on the substrate having the bit line structures. A storage node contact plug is electrically connected to the second contact pad through the insulation layer structure. A storage node electrode, which may be part of a capacitor, is formed on the storage node contact plug. The storage node contact plug has a lower portion and an upper portion having a width wider than that of the lower portion, with vertical sides perpendicular to the first and second directions.

Semiconductor device and method of manufacturing the same

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Seoul, South Korea

Doo-Young Lee