Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Doo-youl Lee

Myeong-Cheol Kim

Gi-Sung Yeo

Han-Ku Cho

Suk-Joo Lee

Pan-suk Kwak

Cha-Won Koh

Sung-Gon Jung

Sang-Su Kim

Sung-Ho Kim

Chang-Jin Kang

Sung-Woo Lee

In-Wook Cho

Jung-hyeon Lee

Man-Hyoung Ryoo

Jin-hee Kim

Si-Hyeung Lee

Sang-Ho Kim

Young Su Kim

Sang-Gyun Woo

Sook Jin Lee

Yool Kang

Yun-Gi Kim

Ji-young Lee

Chang-jin Kang

Seok-Hwan Oh

Kyung-Yub Jeon

Sung-Chan Park

Hak-Sun Lee

Joo-On Park

Min-jong Hong

Jae-ok Yoo

Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

Semiconductor device and layout method for the semiconductor device

A method for manufacturing a solar cell according to an exemplary embodiment includes: forming a first doping film on a substrate; patterning the first doping film so as to form a first doping film pattern and so as to expose a portion of the substrate; forming a diffusion prevention film on the first doping film pattern so as to cover the exposed portion of the substrate; etching the diffusion prevention film so as to form spacers on lateral surfaces of the first doping film pattern; forming a second doping film on the first doping film pattern so as to cover the spacer and exposed substrate; forming a first doping region on the substrate surface by diffusing an impurity from the first doping film pattern into the substrate; and forming a second doping region on the substrate surface by diffusing an impurity from the second doping film pattern into the substrate.

Method for manufacturing solar cell

An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same

A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

Method of forming fine patterns of semiconductor device

Solar cells include a substrate having a light collecting surface thereon and a P-N rectifying junction within the substrate. The P-N rectifying junction includes a base region of first conductivity type (e.g., p-type) and a semiconductor layer of second conductivity type extending between the base region and the light collecting surface. A trench is also provided, which extends through the semiconductor layer and into the base region. First and second electrodes are provided adjacent the light collecting surface. The first electrode is electrically coupled to the semiconductor layer and the second electrode is electrically coupled to the base region, at a location adjacent a bottom of the trench.

Methods of forming semiconductor solar cells having front surface electrodes

A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

Method of forming fine patterns of semiconductor devices using double patterning

A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.

Method for forming fine patterns of a semiconductor device using a double patterning process

A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.

Method of forming a semiconductor device

Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage.

Flash memory device having improved bit-line layout and layout method for the flash memory device

Provided are a flash memory device and a method of manufacturing the same. The flash memory device includes strings. Each of the strings has a string selection line, a ground selection line, and an odd number of word lines formed between the string selection line and the ground selection line.

Flash memory device using double patterning technology and method of manufacturing the same

Disclosed is a semiconductor device having an align key and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a cell area and an align key area. An isolation layer that defines a cell active area is disposed in the cell area of the semiconductor substrate. A cell charge storage layer pattern is disposed across the cell active area. An align charge storage layer pattern is disposed in the align key area of the semiconductor substrate. An align trench self-aligned with the align charge storage layer pattern is formed in the align key area of the semiconductor substrate.

Semiconductor device having align key and method of fabricating the same

In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key

Mask sets are provided which may be used to define a first pattern region that has a first pitch pattern and a second pattern region that has a second pitch pattern during the fabrication of a semiconductor device. These mask sets may include a first mask that has a first exposure region in which a first halftone pattern defines the first pattern region and a first screen region in which a first shield layer covers the second pattern region. These mask sets may further include a second mask that has a second exposure region in which a second halftone pattern defines the second pattern region and a second screen region in which a second shield layer covers the first pattern region. The second shield layer also extends from the second screen region to cover a portion of the second halftone pattern.

Multi-exposure semiconductor fabrication mask sets and methods of fabricating such multi-exposure mask sets

In the method of forming a mask structure, a first mask is formed on a substrate where the first mask includes a first mask pattern having a plurality of mask pattern portions having openings therebetween and a second mask pattern having a corner portion of which an inner side wall that is curved. A sacrificial layer is formed on the first mask. A hard mask layer is formed on the sacrificial layer. After the hard mask layer is partially removed until the sacrificial layer adjacent to the corner portion is exposed, a second mask is formed from the hard mask layer remaining in the space after removing the sacrificial layer. A minute pattern having a fine structure may be easily formed on the substrate.

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Seoul, South Korea

Doo-youl Lee