Samsung Electronics Co., Ltd.

Doo-sup Hwang

Cha-young Yoo

Eun-ae Chung

Satoshi Yamasaki

Kazunobu Tanaka

Tetsuji Yasuda

Kazuyuki Ikuta

Seok-Jun Won

Sang-in Lee

Young-wook Park

Chang-seok Kang

Yong-Kuk Jeong

Wan-don Kim

Hong-bae Park

Cha-Young Yoo

Yun-Jung Lee

Wan-Don Kim

Hag-Ju Cho

Jae-Hyun Joo

Cheol-Seong Hwang

Soon-yeon Park

Young-soh Park

A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Method for manufacturing semiconductor devices and integrated circuit capacitors whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed

A method for manufacturing a capacitor of a semiconductor memory device by controlling thermal budgets is provided. In the method for manufacturing a capacitor of a semiconductor memory device, a lower electrode is formed on a semiconductor substrate. The lower electrode is heat-treated with a first thermal budget. A dielectric layer is formed on the heat-treated lower electrode. The dielectric layer is crystallized by heat-treating the dielectric layer with a second thermal budget which is smaller than the first thermal budget.

Method for manufacturing capacitor of semiconductor memory device controlling thermal budget

Methods and apparatus for plasma annealing layers of a microelectronic capacitor on a substrate are provided to improve the leakage current characteristics of a capacitor and/or to reduce the number of impurities in an electrode.

Methods for forming capacitors on semiconductor substrates

Method for manufacturing a semiconductor device whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed

A mask for a selective growth of a solid, is provided in which the solid is selectively grown in a predetermined region of a substrate and growth on other regions is suppressed. A method is also provided for selectively growing a solid on only the predetermined region of a substrate using the mask. In the mask, a surface layer and an underlayer are provided, each having different chemical compositions. Thus, even if the mask is formed on a substrate in an ultra thin film, the generation of mask defects can be suppressed and stability provided to heat and electron beams.

Mask for the selective growth of a solid, a manufacturing method for the mask, and a method for selectively growing a solid using the mask

A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600&deg; C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900&deg; C., which is higher than the first temperature.

Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment

Mask for the selective growth of a solid

Methods of forming integrated circuit capacitors include the steps of forming an electrically insulating layer on a face of a semiconductor substrate and then patterning the electrically insulating layer to define a contact hole therein. A barrier metal layer is then formed in at least a portion of the contact hole. A lower electrode metal layer is then formed on the barrier metal layer and then planarized by reflowing the lower electrode metal layer at a temperature greater than about 650.degree. C. in a nitrogen gas ambient, to define a lower capacitor electrode. A layer of material having a high dielectric constant is then formed on the lower capacitor electrode. An upper capacitor electrode is then formed on the dielectric layer, opposite the lower capacitor electrode. The dielectric layer may comprise Ba(Sr, Ti)O.sub.3, Pb(Zr, Ti)O.sub.3, Ta.sub.2 O.sub.5, SiO.sub.2, SiN.sub.3, SrTiO.sub.3, PZT, SrBi.sub.2 Ta.sub.2 O.sub.9, (Pb, La)(Zr, Ti)O.sub.3 and Bi.sub.4 Ti.sub.3 O.sub.12. According to one embodiment of the present invention, the step of patterning the electrically insulating layer comprises patterning the electrically insulating layer to define a contact hole therein that exposes the face of the semiconductor substrate. The step of forming a barrier metal layer also preferably comprises depositing a conformal barrier metal layer on sidewalls of the contact hole and on the exposed face of the substrate. The barrier metal layer may be selected from the group consisting of TiN, CoSi, TaSiN, TiSiN, TaSi, TiSi, Ta and TaN.

Methods of forming integrated circuit capacitors using metal reflow

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Kyungki-do, South Korea

Doo-sup Hwang