Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Hyundai Motor Company

Crucialtec Co.ltd

Doo Hwan Lee

Hyoung Joon Kim

Yul Kyo Chung

Seung Eun Lee

Yee Na Shin

Kyung Seob Oh

Jong Rip Kim

Tae Sung Jeong

Jae Hoon Choi

Chang Sup Ryu

Dae Jung Byun

Byung Ho Kim

Kyoung Moo Harr

Joo Young Choi

Jin Yul Kim

Seok Pil Lee

Sung Woo Han

Jin Young Lee

Jae Hak Lee

Jin Seon Park

Suk Hyeon Cho

Tae Je Cho

Seung Chul Oh

Jong Uk Kim

Jung Soo Byun

Ung Hui Shin

Sang Chul Lee

Sung Ki Lim

Yoon Suk Cho

Hyun Kyu Tan

Ju Hyeon Kim

Ho Shik Kang

Byoung Hwa Lee

Myung Sam Kang

Sung Jin Hong

Yong Hoon Kim

Jung Soo Kim

Jin Won Lee

Sung Won Jeong

Dae Hyun Park

Moon Il Kim

Han Seo Cho

Joon Sung Kim

Da Hee Kim

Eun Sil Kim

Jin Yong Ahn

Tae Ho Ko

Yeong A Kim

Tae Kyun Bae

Hwa Sun Park

Sung Hwan Cho

Young Hak Park

Ji Hong Yoo

Hwa Sub Oh

Seon Jun Kim

Seung Gu Kim

Dae Kyu Ahn

Sung Moo Hong

Ho Jin Jung

A method of manufacturing a semiconductor package is provided and includes forming a protective layer on a passivation layer and a connection pad of a semiconductor chip exposed by a first opening of the passivation layer, forming an insulating layer on the protective layer, forming a via hole penetrating the insulating layer to expose the protective layer, forming a second opening by removing a portion of the protective layer through the via hole, and forming a connection via filling the via hole and the second opening and a redistribution layer on the connection via. The second opening and the via hole are connected to have a stepped portion. The first opening has a width narrower closer to the connection pad, and the second opening has a width wider closer to the connection pad.

Semiconductor package

A semiconductor package includes: a semiconductor chip having an active surface, having connection pads disposed thereon, and an inactive surface, opposing the active surface; an encapsulant covering the inactive surface of the semiconductor chip; a thermally conductive via penetrating through at least a portion of the encapsulant on the inactive surface of the semiconductor chip and physically spaced apart from the inactive surface of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads.

Fan-out semiconductor package

A semiconductor package includes a semiconductor chip, an encapsulant, and an interconnection member. The semiconductor chip has connection pads. The encapsulant encapsulates a portion of the semiconductor chip. The interconnection member includes a first insulating layer disposed on the encapsulant and a portion of the semiconductor chip, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the redistribution layer. The redistribution layer is electrically connected to the connection pads of the semiconductor chip, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.

A semiconductor package includes: a semiconductor chip including a passivation film disposed on an active surface and having a first opening exposing at least a portion of a connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening; an encapsulant covering at least a portion of the semiconductor chip; and the connection structure including an insulating layer having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening. The second opening and the via hole are connected to have a stepped portion.

A substrate having an embedded interconnect structure includes an interconnect structure including a circuit member including circuit layers and a passive device disposed in parallel with the circuit member and including an external electrode, and a printed circuit board including an insulating layer covering the interconnect structure, a first wiring layer disposed on the insulating layer, a first wiring via penetrating through at least a portion of the insulating layer and electrically connecting the first wiring layer to an uppermost circuit layer, among the circuit layers, and a second wiring via penetrating through at least a portion of the insulating layer and electrically connecting the first wiring layer to the external electrode of the passive device. A top surface of the uppermost circuit layer, contacting the first wiring via, is coplanar with a top surface of the external electrode, contacting the second wiring via.

Substrate having embedded interconnect structure

A fan-out semiconductor package is provided. A semiconductor chip is disposed in a through hole of a first connection member. At least a portion of the semiconductor chip is encapsulated by an encapsulant. A second connection member including a redistribution layer is formed on an active surface of the semiconductor chip. An external connection terminal having excellent reliability is formed on the encapsulant.

A printed circuit board (PCB) including an embedded electronic component is provided. The printed circuit board includes a core having a cavity, an electronic component inserted into the cavity having a rough surface formed on surfaces of external electrodes provided on both lateral portions thereof, a low rough surface being formed in a portion of the rough surfaces, insulating layers laminated on upper and lower portions of the core and bonded to an outer circumferential surface of the electronic component insertedly positioned in the cavity, and an external circuit pattern provided on the insulating layers.

Method for manufacturing a printed circuit board including an embedded electronic component

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.

A fan-out semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip, an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The heat dissipation member has a thickness greater than that of the semiconductor chip.

A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.

Fan-out semiconductor package and method of manufacturing the fan-out semiconductor

A fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole and having an active surface on which a connection pad is disposed and a non-active surface opposing the active surface; an encapsulant at least partially encapsulating the first connection member and the non-active surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the first connection member includes a first insulating layer, a first redistribution layer embedded in the first insulating layer while contacting the second connection member, and a second redistribution layer disposed on the other side of the first insulating layer opposing one side thereof in which the first redistribution layer is embedded.

Fan-out semiconductor package and manufacturing method thereof

Growing community of inventors

Suwon-si, South Korea

Doo Hwan Lee