Skhynix Inc.

Doo Chan Lee

Jong Yeol Yang

A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Semiconductor memory apparatus

A semiconductor memory apparatus may include a memory bank, row decoders, and an intersection region circuit. The row decoder may be configured to select a dummy block and a plurality of sub blocks based on row address signals, a bank select signal, and a dummy delayed bank select signal. The intersection region circuit may delay the bank select signal and may generate a delayed bank select signal and a dummy delayed bank select signal.

Growing community of inventors

Icheon-si Gyeonggi-do, South Korea

Doo Chan Lee