Ambiq Micro, Inc.

Cadence Design Systems, Inc.

Motorlola, Inc.

Donovan Scott Popps

Stephen James Sheafor

Scott McLean Hanson

Daniel Martin Cermak

Eric Jonathan Deal

Mark A Baur

Amjad Z Qureshi

Frank Arlen Miller

Derrick Andrew Leach

Scott McLean

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very low power microcontroller system

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

Low power autonomous peripheral management

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

Counter/timer array for generation of complex patterns independent of software control

A system-on-chip (SOC) () is interfaced with a memory () formed by a plurality of stacked memory integrated circuit dies (-). The SOC () includes a memory controller () that has a built-in self-test (BIST) system () for performing the testing and repair of memory (). BIST system () includes a microcode processor () that communicates externally to the SOC () through a Joint Test Action Group interface () and is coupled to a BIST state machine () for executing a memory specific test sequence to detect faults in memory (). The microcode processor () further communicates with a repair state machine () to execute memory specific repair procedures responsive to memory faults being detected.

Apparatus and method for built-in test and repair of 3D-IC memory

A synchronous pipelined burst memory (20) achieves high speed by violating conventional pipelining rules. The memory (20) includes an address register (24) which latches a burst address during a first cycle of a periodic clock signal. The burst address is driven to an input of an asynchronous memory core (40), but output data from the asynchronous memory core (40) is not latched until a third cycle of the periodic clock signal which occurs after a second cycle of the periodic clock signal which is immediately subsequent to the first cycle. The memory (20) outputs successive data elements of the burst during consecutive cycles of the periodic clock signal to complete the burst cycle.

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Austin, TX, United States of America

Donovan Scott Popps