Motorola Corporation

Donovan L Raatz

Taisheng Feng

Stephen T Flannagan

Ray Chang

Lawrence F Childs

Kenneth W Jones

Alan Richard Bormann

A cache TAG RAM (20) has a TAG array (22, 24) for storing TAG addresses of data stored in a cache memory, and a valid bit array (26, 31). In the cache TAG RAM (20), a valid bit is set for each TAG address to indicate if the TAG address is valid. The valid bit array (26, 31) is located separate from the TAG array (22, 24). During power-up of the cache TAG RAM (20), a multiple step invalidation cycle is used to sequentially invalidate groups of columns of the valid bit array (26, 31). The multiple step invalidation cycle reduces the peak current during an invalidation cycle, thus reducing metal migration.

Cache tag RAM having separate valid bit array with multiple step

A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.

Layout for noise reduction on a reference voltage

An integrated circuit memory (20) has a write pulse generator (38) for generating a self-timed write pulse independent of system clock frequency and system clock duty cycle. The write pulse generator (38) includes a delay element (56) and a delay element (68). The write pulse is triggered on a rising edge of the clock signal and has a duration that is determined by a delay time provided by the delay element (68). The delay elements (56, 68) provide single-sided delays and compensate for process, power supply, temperature variations of the integrated circuit memory (20).

Integrated circuit memory having a self-timed write pulse independent of

A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

BICMOS output buffer circuit having overshoot protection

A power-on reset circuit (30) for a memory (20) includes a DC model circuit (39), an N.sub.BIAS check circuit (64), and a NAND logic gate (71). A logic low power-on reset signal is provided at power-up of the memory (20) to establish initial conditions in a clock circuit (29) and in row and column predecoders/latches (24, 27). When the power supply voltage, a bandgap reference voltage, and a bias voltage all reach their predetermined voltages, the power-on reset circuit (30) provides a logic high power-on reset signal. In this manner, the power-on reset circuit (30) is assured of providing a logic low power-on reset signal until all of the proper voltage levels are reached. In addition, the power-on reset circuit models a DC circuit equivalent of an address buffer circuit (79) for compensating for process and temperature variations.

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Austin, TX, United States of America

Donovan L Raatz