Massachusetts Institute of Technology

Donna-Ruth Webb Yost

Rabindra N Das

Mark A Gouker

Andrew J Kerman

William D Oliver

Danna Rosenberg

Keith Warner

Chenson K Chen

Craig L Keast

Steven A Vitale

Melissa Alyson Smith

Todd A Thorsen

Christopher W Leitz

Paulo C Lozano

Daniel Kenneth Freeman

Vladimir Bolkhovsky

James A Gregory

Reuel Bennett Swint

Boris G Kharas

Kevin Ryu

Jonilyn L Yoder

Renee D Lambert

Mollie Schwartz

Wayne Woods

Richard P D'Onofrio

Thomas Hazard

Justin Mallek

Cyrus Hirjibehedin

Noah Siegel

Gregory D Allen

Electrospray devices and methods of fabricating electrospray devices are described.

Electrospray devices and methods for fabricating electrospray devices

Qubit circuits having components formed deep in a substrate are described. The qubit circuits can be manufactured using existing integrated-circuit technologies. By forming components such as superconducting current loops, inductive, and/or capacitive components deep in the substrate, the footprint of the qubit circuit integrated within the substrate can be reduced. Additionally, coupling efficiency to and from the qubit can be improved and losses in the qubit circuit may be reduced.

Qubit circuits with deep, in-substrate components

In some embodiments, a self-aligned electrospray device can include a silicon wafer, a fluid reservoir, and a circuit. The silicon wafer can have a layer of electrically insulating material deposited on a top surface and a deposited layer of electrically conducting material. The silicon wafer and the deposited layers can have through holes. The electrically insulating layer may be undercut. The fluid reservoir can be mounted to a bottom surface of the silicon wafer for containing fluid. The circuit can provide an electric potential difference and be coupled between the layer of electrically conducting material and the fluid reservoir.

Self-aligned electrospray device and related manufacturing techniques

A new process that enables void-free direct-bonded MBE-passivated large-format image sensors is disclosed. This process can be used to produce thin large-area image sensors for UV and soft x-ray imaging. Such devices may be valuable in future astronomy missions or in the radiology field. Importantly, by controlling the hydrogen concentration in the silicon oxide layers of the image sensor and the support wafer, voids in the bonding interface can be significantly reduced or eliminated. This process can be applied to any wafer that includes active circuitry and requires a second wafer, such as a support wafer.

Semiconductor surface passivation

A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

Electrical and electromechanical devices often require maintaining a specific temperature, or a narrow range or temperatures, during operation. An assembly regulates the temperature of a device by providing a variable thermal resistance between the device and a heatsink. The device can be mounted to a base having a high thermal resistance, the base thermally isolating the device from the heatsink. At low environmental temperatures, the base enables the device to rise to its operating temperature as a result of the device's waste heat, and with no or minimal use of a heater. As the environmental temperature increases, a working fluid, having a low thermal resistance, undergoes thermal expansion to fill a portion of a volume in the base between the device and the heat sink, lowering the thermal resistance between the device and the heatsink to maintain the device at the required operating temperature.

Variable thermal resistance

Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).

Shielded through via structures and methods for fabricating shielded through via structures

A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.

Qubit and coupler circuit structures and coupling techniques

A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.

Interconnect structures and methods for fabricating interconnect structures

A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.

Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure

In a system for aligning at least two semiconductor structures for coupling, an alignment device includes a mounting structure having at least first and second opposing portions. The alignment device also includes a first mounting portion movably coupled to the first portion of the mounting structure, the first mounting portion configured to couple to a first surface of a first semiconductor structure. The alignment device additionally includes a second mounting portion movably coupled to the second portion of the mounting structure, the second mounting portion configured to couple to a second surface of a second semiconductor structure. The alignment device further includes one or more imaging devices disposed above at least one of the first and second mounting portions of the alignment device, the imaging devices configured to capture and/or or detect alignment marks in at least the first semiconductor structure. A corresponding method for aligning two or more semiconductor structures for coupling is also provided.

Systems and methods for aligning and coupling semiconductor structures

A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.

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Acton, MA, United States of America

Donna-Ruth Webb Yost