International Business Machines Corporation

Other

Siemens Aktiengesellschaft

Donna Rizzone Cote

Son Van Nguyen

Ronald A Warren

David Stanasolovich

Timothy Joseph Dalton

Kevin Shawn Petrarca

Richard Paul Volant

Richard Anthony Conti

Christopher Joseph Waskiewicz

Robert Allen Groves

Kenneth Jay Stein

Seshadri Subbanna

John C Bisson

Daniel C Edelstein

Keith Kwong Hon Wong

Ravikumar Ramachandran

John C Forster

John Anthony Fitzsimmons

Chandrasekhar Narayan

Paul Charles Jamison

David M Dobuzinsky

William J Cote

Max Gerald Levy

Ashima B Chakravarti

Dragan Valentin Podlesnik

Axel Christoph Brintzinger

Markus M Kirchhoff

Ernest N Levine

Thomas S Rupp

Kenneth C Arndt

Thomas H Ivers

Anthony J Konecni

Virinder S Grewal

Frank V Liucci

Manfred Hauf

Donna Diane Miura

Senthil K Srinivasan

William Joseph Cote

Ronald W Mauthe

An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (AN), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less than 1.0, and a second layer adhered to the first layer, the second layer including a nitride (AN), where y is greater than or equal to 1.0. The multiple layer electrode allows the first layer to better adhere to chalcogenide based memory material, such as GST, than for example, stoichiometric TiN or WN, which prevents delamination. A phase change memory device and method are also disclosed.

Electrode for phase change memory device and method

A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Method of fabricating micro-electromechanical switches on CMOS compatible substrates

A layer of doped oxide glass is deposited on a semiconductor device in a chemical vapor deposition chamber by reacting gaseous sources of silicon, ozone and at least one boron or phosphorus dopant in a carrier gas, the ozone being present in a ratio of about 9-15 weight percent of the carrier gas. The deposited layer of doped oxide glass contains no greater than about 4 weight percent each of boron and phosphorus concentration and is annealed at a temperature no greater than about 700&deg; C. for a time sufficient to soften and outgas any residual moisture in the oxide glass layer and level the upper surface to a desired degree.

Low temperature/low dopant oxide glass film

A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.

Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states

A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

Manufacturing of cavity fuses on gate conductor level

The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride.

Adhesion of silicon carbide films

Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.

Methods and apparatus for filling high aspect ratio structures with

In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Process for reducing circuit damage during PECVD in single wafer PECVD

A spin on insulating coating with ionic barrier properties is formed on a substrate, by mixing a P or B containing material such as phosphazene or borazine with a solution of silsesquioxane, spin coating on a substrate to form a film of pre-determined thickness. The coated film is cured in a step wise manner to drive out the solvents and most of the H and OH groups, with the resulting film having a composition SiONX, where X can be B, P, F and mixtures thereof. The amount of P, B or other elements are predetermined by calculating the solids in the silsesquioxane and adding suitable amount of borazine or phosphazene. The coated and cured film fills and planarizes any topography on the substrate created by etching trenches, forming gate stacks or metal lines. In one of the variation, the substrate has a layer of insulating material disposed thereon prior to the application of the spin-on insulator.

Flowable spin-on insulator

An inert gas, such as helium, nitrogen, or argon, is used for pressurization and stabilization in a chemical vapor deposition process that occurs in an ambient temperature in excess of 400.degree. C. Using the inert gas in the pressurization and stabilization stages of the chemical vapor deposition process eliminates the formation of tungsten oxides on tungsten studs, lines and other devices in the substrate, thereby eliminating the variable contact resistance and other problems associated with tungsten oxides.

Process for the elimination of tungsten oxidation with inert gas

A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Self-aligned contact studs for semiconductor structures

Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.

Selective etching process for boron nitride films

Self-aligning process for fabricating a semiconductor structure and stud therefor on a semiconductor substrate comprises depositing a first material onto the substrate, depositing a second material onto the first material, removing excess portions of second material so as to form openings through the second material exposing excess portions of first material, whereby a selected portion of second material is retained and forms a sacrificial element, removing the excess portions of first material selectively to the substrate so as to extend the openings through the first material to the substrate, whereby a selected portion of first material is retained and forms the semiconductor structure, filling the openings with an insulating material, removing the sacrificial element selectively to the insulating material and the semiconductor structure for forming a contact window opening for allowing access to the semiconductor structure, and filling the contact window opening with stud material so as to contact the semiconductor structure for forming the stud.

Process for fabrication of a semiconductor structure and contact stud

Growing community of inventors

Poughkeepsie, NY, United States of America

Donna Rizzone Cote