International Business Machines Corporation

Donna Kaye Johnson

Jerome Brett Lasky

Kirk David Peterson

Arne Watson Ballantine

Peter James Lindgren

Mary Conroy Bushey

David Paul Agnello

Douglas Duane Coolbaugh

Glen L Miles

Glenn Robert Miller

Kevin K Chan

James William Adkisson

Michael Joseph Zierak

Peter B Gray

Peter John Geiss

Shwu-Jen Jeng

Tina Jane Wagner

Jeffrey D Gilbert

Robb Allen Johnson

James J Toomey

George A Dunbar, Iii

Glenn C MacDougall

James V Hart, Iii

Matthew D Gallagher

Jean-Jacques H Psaute

Bernard A Roque, Jr

Arne Watson Ballamine

Jim S Nakos

A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.

Cobal disilicide structure

A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of cobalt monosilicide, with substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may alternatively comprise a layer of cobalt disilicide, a patch of an oxide of titanium, and a reagent in contact with the patch at a temperature and for a period of time. The layer is substantially free of cobalt monosilicide. The patch is on the layer of cobalt disilicide. The reagent is adapted to remove the patch within the period of time. The reagent does not chemically react with the layer of cobalt disilicide, and the reagent comprises water, ammonium hydroxide, and hydrogen peroxide.

Cobalt disilicide structure

An apparatus for holding a semiconductor substrate comprises a plate having a pocket which holds the substrate, wherein the pocket comprises a lower surface and an inner edge. The inner edge comprises a plurality of members extending radially inward to reduce the area of contact between the inner edge and the substrate. The beveled edge is inclined so that there is an acute angle between the lower surface of the pocket and the beveled edge.

Susceptor pocket with beveled projection sidewall

A SiGe heterojunction bipolar transistor including at least an emitter formed on a SiGe base region wherein the sidewalls of the emitter are protected by a conformal passivation layer. The conformal passivation layer is formed on the exposed sidewalls of said emitter prior to siliciding the structure. The presence of the passivation layer in the structure prevents silicide shorts from occurring by eliminating bridging between adjacent silicide regions; therefore improved SiGe bipolar yield is obtained. A method for forming such a structure is also provided.

Passivation for improved bipolar yield

A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Structure and method for formation of a blocked silicide resistor

A method and structure for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across a wafer surface. A substrate that includes a semiconductor material and a first dopant, has an amorphous layer formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. Heating of the wafer at 450 to 625 degree C. recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.

Semiconductor temperature monitor

A method, and associated structure, for fabricating a semiconductor wafer that may be used to monitor the temperature distribution across the wafer surface. Given a substrate that includes a semiconductor material and a first dopant, an amorphous layer is formed from a top portion of the substrate, and the amorphous layer is doped with a second dopant of polarity opposite to a polarity of the first dopant. The amorphous layer may be formed by directing an ionic species, such as ionic germanium, into the top portion of the substrate. Alternatively, particular second dopants, such as arsenic, may serve to also amorphize the top portion of the substrate. Next, the wafer is heated to a temperature in a range of 450 to 625&deg; C. The heating of the wafer recrystallizes a portion of the amorphous layer that is adjacent to the substrate at a recrystallization rate that depends on a local temperature on the wafer surface. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the recrystallized layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer. The measured spatial distribution of sheet resistance may be utilized to readjust the spatial distribution of heat input to another wafer in order to achieve a more uniform temperature across the other wafer's surface.

A method for removing a formation of oxide of titanium that is generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The method applies a chemical reagent to the FET at a predetermined temperature, and for a predetermined period of time, necessary for removing the formation, wherein the reagent does not chemically react with the cobalt disilicide. A reagent that accomplishes this task comprises water (H O), ammonium hydroxide (NH OH), and hydrogen peroxide (H O ), wherein the NH OH and the H O each comprise approximately 4% of the total reagent volume. An effective temperature is 65&deg; C. combined with a 3 minute period of application.

Wet cleans for cobalt disilicide processing

The dark current defects in a charge couple device are reduced by employing a hydrogen anneal followed by depositing a silicon nitride barrier layer by RTCVD.

Method for reducing dark current effects in a charge couple device

Reliable HTO (High Temperature Oxide) dielectrics are provide by a rapid thermal chemical vapor deposition (RTCVD) process in which a low pressure and a high ratio of reactants, e.g., oxygen-containing gas to silane-containing gas, is employed. Specifically, the reliable HTO is formed by a rapid thermal chemical vapor deposition at temperatures of from about 500&deg; C. or above, said rapid thermal chemical vapor deposition process being carried out at a pressure of less than 80 Torr and in the presence of at least one oxygen-containing reactant and at least one silane-containing reactant, said reactants having a ratio of oxygen-containing to silane-containing of about 25:1 or greater. Semiconductor devices such as capacitors and transistors that include at least a layer of the high temperature oxide of the present invention used as a dielectric material are also provided.

Growing community of inventors

Underhill, VT, United States of America

Donna Kaye Johnson