Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Microchip Technology Inc.

Donia Sebastian

Xin Guo

David J Pelster

Aliasgar S Madraswala

David B Carlton

Curtis A Gittens

Yogesh B Wakchaure

Scott Nelson

Neelesh Vemula

Ihab Jaser

Mark Anthony Golez

Simon Ramage

Kai-Uwe Schmidt

Kwok Kong

Ali Khakifirooz

Pranav Kalavade

Ravi H Motwani

Lei Chen

Rohit Sudhir Shenoy

Yu Du

William Brent Wilson

Jack Wynne

Varsha Regulapati

Naga Kiranmayee Upadhyayula

Dan McLeran

Shu-Jen Lee

Aaron Lutzker

Chu-hsiang Teng

Systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency. Control circuitry then detect a second workload value for the circuit, which is less than the first workload value. When the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency which is greater than the first clock frequency. The control circuitry then causes the circuit to operate at the second clock frequency.

Methods and systems to dynamically improve low task storage depth latency in a solid-state drive device

An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request's target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.

System and method for centralized management of workload and parallel service of prioritized requests

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Solid state drive with multiplexed internal channel access during program data transfers

Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.

Programmable and high-performance data scrambler for non-volatile memory controllers

A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user. The multi-user arbitration algorithm includes (a) selecting an intra-user winning function queue for each respective user by performing an intra-user function queue arbitration of the function queues associated with the respective user based on the function queue categorizations associated with the arbitrated function queues, (b) selecting an inter-user winning function queue by performing an inter-user function queue arbitration of the intra-user winning function queues selected for the multiple users, and (c) serving a function from the inter-user winning function queue to the memory resource.

System for managing access to a memory resource by multiple users

Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Independent NAND memory operations by plane

Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.

Techniques to a set voltage level for a data access

A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.

Method and apparatus to prioritize read response time in a power-limited storage device

A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

Coarse pass and fine pass multi-level NVM programming

In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.

Power management and monitoring for storage devices

Growing community of inventors

Fair Oaks, CA, United States of America

Donia Sebastian